From 855ad0c9b3e9ea03f34c70332a2175cd604acf6c Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Tue, 29 Dec 2020 15:41:35 +0800 Subject: [PATCH] MLK-25915-1 arm64: dts: imx8m: set the parent clock of pcie aux clock Set the parent clock for PCIE_AUX clock firstly, then set the rate of the PCI_AUX clock to 10MHZ. Signed-off-by: Richard Zhu Reviewed-by: Peter Chen (cherry picked from commit c787efe575330e538cc92da0dde49255bdc80c94) --- arch/arm64/boot/dts/freescale/imx8mm-evk.dts | 6 ++++++ arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 2 ++ arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 9 +++++++++ 3 files changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts index 08bfdda7cdba02..f5591be728aec8 100755 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts @@ -230,6 +230,9 @@ <&clk IMX8MM_CLK_PCIE1_PHY>, <&pcie0_refclk>; clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>; + assigned-clock-rates = <10000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>; ext_osc = <1>; status = "okay"; }; @@ -242,6 +245,9 @@ <&clk IMX8MM_CLK_PCIE1_PHY>, <&pcie0_refclk>; clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>; + assigned-clock-rates = <10000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>; ext_osc = <1>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index 85f8fe4a78bc65..91d926cfb5dd27 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -686,6 +686,7 @@ clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI_SRC>, <&clk IMX8MP_CLK_PCIE_AUX>; + assigned-clock-rates = <500000000>, <10000000>; assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>, <&clk IMX8MP_SYS_PLL2_50M>; status = "okay"; @@ -702,6 +703,7 @@ clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI_SRC>, <&clk IMX8MP_CLK_PCIE_AUX>; + assigned-clock-rates = <500000000>, <10000000>; assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>, <&clk IMX8MP_SYS_PLL2_50M>; status = "disabled"; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index 29bbcffdbb151c..cd84f5679eee00 100755 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -662,6 +662,9 @@ <&clk IMX8MQ_CLK_PCIE1_PHY>, <&pcie0_refclk>; clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + assigned-clocks = <&clk IMX8MQ_CLK_PCIE1_AUX>; + assigned-clock-rates = <10000000>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_50M>; hard-wired = <1>; status = "okay"; }; @@ -676,6 +679,9 @@ <&clk IMX8MQ_CLK_PCIE2_PHY>, <&pcie1_refclk>; clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_AUX>; + assigned-clock-rates = <10000000>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_50M>; status = "okay"; }; @@ -687,6 +693,9 @@ <&clk IMX8MQ_CLK_PCIE2_PHY>, <&pcie1_refclk>; clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_AUX>; + assigned-clock-rates = <10000000>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_50M>; status = "disabled"; };