diff --git a/Source/HBIOS/cfg_master.asm b/Source/HBIOS/cfg_master.asm
index fb57e607..22e0f27b 100644
--- a/Source/HBIOS/cfg_master.asm
+++ b/Source/HBIOS/cfg_master.asm
@@ -269,7 +269,7 @@ PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 PPIDE1BASE	.EQU	$20		; PPIDE 1: PPI REGISTERS BASE ADR
 PPIDE1A8BIT	.EQU	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
 PPIDE1B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
-PPIDE2BASE	.EQU	$44		; PPIDE 2: PPI REGISTERS BASE ADR
+PPIDE2BASE	.EQU	$14		; PPIDE 2: PPI REGISTERS BASE ADR
 PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
diff --git a/Source/HBIOS/cfg_mbc.asm b/Source/HBIOS/cfg_mbc.asm
index 8f0669d7..048a4b9b 100644
--- a/Source/HBIOS/cfg_mbc.asm
+++ b/Source/HBIOS/cfg_mbc.asm
@@ -198,7 +198,7 @@ PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 PPIDE1BASE	.EQU	$20		; PPIDE 1: PPI REGISTERS BASE ADR
 PPIDE1A8BIT	.EQU	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
 PPIDE1B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
-PPIDE2BASE	.EQU	$44		; PPIDE 2: PPI REGISTERS BASE ADR
+PPIDE2BASE	.EQU	$14		; PPIDE 2: PPI REGISTERS BASE ADR
 PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
diff --git a/Source/HBIOS/cfg_mk4.asm b/Source/HBIOS/cfg_mk4.asm
index e642ce5c..466e84ff 100644
--- a/Source/HBIOS/cfg_mk4.asm
+++ b/Source/HBIOS/cfg_mk4.asm
@@ -191,7 +191,7 @@ IDE2B8BIT	.EQU	FALSE		; IDE 2B (MASTER): 8 BIT XFER
 PPIDEENABLE	.EQU	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
 PPIDETRACE	.EQU	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 PPIDECNT	.EQU	2		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
-PPIDE0BASE	.EQU	$44		; PPIDE 0: PPI REGISTERS BASE ADR
+PPIDE0BASE	.EQU	$14		; PPIDE 0: PPI REGISTERS BASE ADR
 PPIDE0A8BIT	.EQU	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
 PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 PPIDE1BASE	.EQU	$20		; PPIDE 1: PPI REGISTERS BASE ADR
diff --git a/Source/HBIOS/cfg_sbc.asm b/Source/HBIOS/cfg_sbc.asm
index f44de4cb..6295cb71 100644
--- a/Source/HBIOS/cfg_sbc.asm
+++ b/Source/HBIOS/cfg_sbc.asm
@@ -198,7 +198,7 @@ PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 PPIDE1BASE	.EQU	$20		; PPIDE 1: PPI REGISTERS BASE ADR
 PPIDE1A8BIT	.EQU	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
 PPIDE1B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
-PPIDE2BASE	.EQU	$44		; PPIDE 2: PPI REGISTERS BASE ADR
+PPIDE2BASE	.EQU	$14		; PPIDE 2: PPI REGISTERS BASE ADR
 PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
 PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
diff --git a/Source/HBIOS/dsrtc.asm b/Source/HBIOS/dsrtc.asm
index 9b8c630d..c4e8608b 100644
--- a/Source/HBIOS/dsrtc.asm
+++ b/Source/HBIOS/dsrtc.asm
@@ -118,7 +118,7 @@ DS2d8k		.EQU	%10101011	; 2 DIODES 8K RESISTOR
 ;
 #IF (DSRTCMODE == DSRTCMODE_MFPIC)
 ;
-DSRTC_IO	.EQU	$43		; RTC PORT ON MF/PIC
+DSRTC_IO	.EQU	$13		; RTC PORT ON MF/PIC
 ;
 DSRTC_DATA	.EQU	%00000001	; BIT 0 IS RTC DATA OUT
 DSRTC_CLK	.EQU	%00000100	; BIT 2 IS RTC CLOCK (CLK)
diff --git a/Source/HBIOS/uart.asm b/Source/HBIOS/uart.asm
index 4045a6e9..c8e0b9b2 100644
--- a/Source/HBIOS/uart.asm
+++ b/Source/HBIOS/uart.asm
@@ -55,7 +55,7 @@ UART_AFCACT		.EQU	5	; AUTO FLOW CONTROL ACTIVE BIT
 ;
 UARTSBASE		.EQU	$68
 UARTCBASE		.EQU	$80
-UARTMBASE		.EQU	$48
+UARTMBASE		.EQU	$18
 UART4BASE		.EQU	$C0
 UARTRBASE		.EQU	$A0
 UARTDBASE		.EQU	$80
diff --git a/Source/ver.inc b/Source/ver.inc
index 90b2cbf3..d28d93cf 100644
--- a/Source/ver.inc
+++ b/Source/ver.inc
@@ -2,4 +2,4 @@
 #DEFINE	RMN	1
 #DEFINE	RUP	1
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"3.1.1-pre.178"
+#DEFINE BIOSVER	"3.1.1-pre.179"
diff --git a/Source/ver.lib b/Source/ver.lib
index 0814c961..17bcfe0b 100644
--- a/Source/ver.lib
+++ b/Source/ver.lib
@@ -3,5 +3,5 @@ rmn	equ	1
 rup	equ	1
 rtp	equ	0
 biosver	macro
-	db	"3.1.1-pre.178"
+	db	"3.1.1-pre.179"
 	endm