Skip to content

Commit 3027cb5

Browse files
ibmthidcrowell77
ibmthi
authored and
dcrowell77
committed
L3 Update - p9_hcd_cache_stopclocks HWP
Change-Id: Id2d05ebed42c6456557f88917e1b8f9c1a8daf00 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45735 Tested-by: FSP CI Jenkins <[email protected]> Tested-by: Jenkins Server <[email protected]> Tested-by: PPE CI <[email protected]> Tested-by: Hostboot CI <[email protected]> Reviewed-by: YUE DU <[email protected]> Reviewed-by: Gregory S. Still <[email protected]> Reviewed-by: Jennifer A. Stofer <[email protected]> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45744 Reviewed-by: Hostboot Team <[email protected]> Tested-by: Jenkins OP Build CI <[email protected]> Tested-by: Jenkins OP HW <[email protected]> Reviewed-by: Daniel M. Crowell <[email protected]>
1 parent 72b46fb commit 3027cb5

File tree

6 files changed

+208
-39
lines changed

6 files changed

+208
-39
lines changed

‎src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.C

+24-23
Original file line numberDiff line numberDiff line change
@@ -30,26 +30,25 @@
3030

3131
// *HWP HWP Owner : David Du <[email protected]>
3232
// *HWP Backup HWP Owner : Greg Still <[email protected]>
33-
// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com>
33+
// *HWP FW Owner : Amit Tendolkar <amit.tendolkar@in.ibm.com>
3434
// *HWP Team : PM
3535
// *HWP Consumed by : HB:PERV
36-
// *HWP Level : 2
36+
// *HWP Level : 3
3737

3838
//------------------------------------------------------------------------------
3939
// Includes
4040
//------------------------------------------------------------------------------
41-
4241
#include <p9_misc_scom_addresses.H>
4342
#include <p9_quad_scom_addresses.H>
4443
#include <p9_hcd_common.H>
4544
#include <p9_common_clk_ctrl_state.H>
46-
#include "p9_hcd_l2_stopclocks.H"
47-
#include "p9_hcd_cache_stopclocks.H"
45+
#include <p9_hcd_l2_stopclocks.H>
46+
#include <p9_hcd_cache_stopclocks.H>
47+
#include <p9_quad_scom_addresses_fld.H>
4848

4949
//------------------------------------------------------------------------------
5050
// Constant Definitions
5151
//------------------------------------------------------------------------------
52-
5352
enum P9_HCD_CACHE_STOPCLOCKS_CONSTANTS
5453
{
5554
CACHE_CLK_STOP_POLLING_HW_NS_DELAY = 10000,
@@ -62,7 +61,7 @@ enum P9_HCD_CACHE_STOPCLOCKS_CONSTANTS
6261
//------------------------------------------------------------------------------
6362
// Procedure: Quad Clock Stop
6463
//------------------------------------------------------------------------------
65-
64+
// See doxygen in header file
6665
fapi2::ReturnCode
6766
p9_hcd_cache_stopclocks(
6867
const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target,
@@ -99,7 +98,7 @@ p9_hcd_cache_stopclocks(
9998
// region including PBIEQ clock domain is being stopped, which
10099
// incidentally should always be the case for MPIPL
101100
l_data64.flush<0>();
102-
l_data64.setBit<30>();
101+
l_data64.setBit<EQ_QPPM_QCCR_PB_PURGE_REQ>();
103102
// Set bit 30 in EQ_QPPM_QCCR_SCOM2(100F01BF) Reg, Pulse to the
104103
// Powerbus logic in the Cache clock domain to request them to purge
105104
// their async buffers in preparation to power off the Quad
@@ -113,9 +112,8 @@ p9_hcd_cache_stopclocks(
113112
// Acknowledgement from Powerbus that the buffers are empty
114113
// and can safely be fenced & clocked off.
115114
FAPI_TRY(fapi2::getScom(i_target, EQ_QPPM_QCCR_SCOM, l_data64));
116-
bool l_poll_data = l_data64.getBit<31>();
117115

118-
if(l_poll_data == 1)
116+
if(l_data64.getBit<EQ_QPPM_QCCR_PB_PURGE_DONE_LVL>())
119117
{
120118
break;
121119
}
@@ -131,18 +129,19 @@ p9_hcd_cache_stopclocks(
131129
fapi2::QPPM_QCCR_PB_PURGE_DONE_LVL_TIMEOUT()
132130
.set_TARGET(i_target)
133131
.set_EQPPMQCCR(l_data64),
134-
"QPPM_QCCR_PB_PURGE_DONE_LVL Reg bit 31 not set.");
132+
"QPPM_QCCR_PB_PURGE_DONE_LVL Reg bit _QPPM_QCCR_PB_PURGE_DONE_LVL not set.");
135133

134+
// Clear purge request
136135
l_data64.flush<0>();
137-
l_data64.setBit<30>();
136+
l_data64.setBit<EQ_QPPM_QCCR_PB_PURGE_REQ>();
138137
FAPI_TRY(fapi2::putScom(i_target, EQ_QPPM_QCCR_SCOM1, l_data64));
139138
}
140139

141140
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_VDM_ENABLED, l_chip,
142141
l_attr_vdm_enabled));
143142
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_perv,
144143
l_attr_chip_unit_pos));
145-
// l_attr_chip_unit_pos = l_attr_chip_unit_pos - p9hcd::PERV_TO_QUAD_POS_OFFSET;
144+
// l_attr_chip_unit_pos = l_attr_chip_unit_pos - p9hcd::PERV_TO_QUAD_POS_OFFSET;
146145
l_attr_chip_unit_pos = l_attr_chip_unit_pos - 0x10;
147146

148147
if (i_select_regions & p9hcd::CLK_REGION_EX0_L3)
@@ -161,10 +160,9 @@ p9_hcd_cache_stopclocks(
161160
FAPI_DBG("Check PM_RESET_STATE_INDICATOR via GPMMR[15]");
162161
FAPI_TRY(getScom(i_target, EQ_PPM_GPMMR_SCOM, l_data64));
163162

164-
if (!l_data64.getBit<15>())
163+
if (!l_data64.getBit<EQ_PPM_GPMMR_RESET_STATE_INDICATOR>())
165164
{
166165
FAPI_DBG("Gracefully turn off power management, if fail, continue anyways");
167-
/// @todo RTC158181 suspend_pm()
168166
}
169167

170168
FAPI_DBG("Check cache clock controller status");
@@ -182,15 +180,15 @@ p9_hcd_cache_stopclocks(
182180
FAPI_DBG("Check PERV fence status for access to CME via CPLT_CTRL1[4]");
183181
FAPI_TRY(getScom(i_target, EQ_CPLT_CTRL1, l_temp64));
184182

185-
if (l_data64.getBit<4>() == 0 && l_temp64.getBit<4>() == 0)
183+
if (l_data64.getBit<EQ_CLOCK_STAT_SL_STATUS_PERV>() == 0 &&
184+
l_temp64.getBit<EQ_CPLT_CTRL1_TC_PERV_REGION_FENCE>() == 0)
186185
{
187-
/// @todo RTC158181 disable l2 snoop? disable lco? assert refresh quiesce?
188186
FAPI_DBG("Assert L3 pscom masks via RING_FENCE_MASK_LATCH_REG[4-9]");
189187
FAPI_TRY(putScom(i_target, EQ_RING_FENCE_MASK_LATCH_REG, l_l3mask_pscom));
190188
}
191189

192190
FAPI_DBG("Assert chiplet fence via NET_CTRL0[18]");
193-
FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WOR, MASK_SET(18)));
191+
FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WOR, MASK_SET(EQ_NET_CTRL0_FENCE_EN)));
194192

195193
// -------------------------------
196194
// Stop L2 clocks
@@ -247,17 +245,21 @@ p9_hcd_cache_stopclocks(
247245

248246
FAPI_TRY(getScom(i_target, EQ_CPLT_STAT0, l_data64));
249247
}
250-
while((l_data64.getBit<8>() != 1) && ((--l_loops1ms) != 0));
248+
while((!l_data64.getBit<EQ_CPLT_STAT0_CC_CTRL_OPCG_DONE_DC>()) && ((--l_loops1ms) != 0));
251249

252250
FAPI_ASSERT((l_loops1ms != 0),
253-
fapi2::PMPROC_CACHECLKSTOP_TIMEOUT().set_EQCPLTSTAT(l_data64),
251+
fapi2::PMPROC_CACHECLKSTOP_TIMEOUT()
252+
.set_TARGET(i_target)
253+
.set_EQCPLTSTAT(l_data64),
254254
"Cache Clock Stop Timeout");
255255

256256
FAPI_DBG("Check cache clocks stopped");
257257
FAPI_TRY(getScom(i_target, EQ_CLOCK_STAT_SL, l_data64));
258258

259259
FAPI_ASSERT((((~l_data64) & l_region_clock) == 0),
260-
fapi2::PMPROC_CACHECLKSTOP_FAILED().set_EQCLKSTAT(l_data64),
260+
fapi2::PMPROC_CACHECLKSTOP_FAILED()
261+
.set_TARGET(i_target)
262+
.set_EQCLKSTAT(l_data64),
261263
"Cache Clock Stop Failed");
262264
FAPI_DBG("Cache clocks stopped now");
263265

@@ -266,7 +268,7 @@ p9_hcd_cache_stopclocks(
266268
// -------------------------------
267269

268270
FAPI_DBG("Assert vital fence via CPLT_CTRL1[3]");
269-
FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL1_OR, MASK_SET(3)));
271+
FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL1_OR, MASK_SET(EQ_CPLT_CTRL1_TC_VITL_REGION_FENCE)));
270272

271273
l_region_fence = l_region_clock;
272274

@@ -356,4 +358,3 @@ fapi_try_exit:
356358
FAPI_INF("<<p9_hcd_cache_stopclocks");
357359
return fapi2::current_err;
358360
}
359-

‎src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.H

+2-2
Original file line numberDiff line numberDiff line change
@@ -29,10 +29,10 @@
2929

3030
// *HWP HWP Owner : David Du <[email protected]>
3131
// *HWP Backup HWP Owner : Greg Still <[email protected]>
32-
// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com>
32+
// *HWP FW Owner : Amit Tendolkar <amit.tendolkar@in.ibm.com>
3333
// *HWP Team : PM
3434
// *HWP Consumed by : HB:PERV
35-
// *HWP Level : 2
35+
// *HWP Level : 3
3636

3737
#ifndef __P9_HCD_CACHE_STOPCLOCKS_H__
3838
#define __P9_HCD_CACHE_STOPCLOCKS_H__

‎src/import/chips/p9/procedures/hwp/cache/p9_hcd_l2_stopclocks.C

+18-10
Original file line numberDiff line numberDiff line change
@@ -30,10 +30,10 @@
3030

3131
// *HWP HWP Owner : David Du <[email protected]>
3232
// *HWP Backup HWP Owner : Greg Still <[email protected]>
33-
// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com>
33+
// *HWP FW Owner : Amit Tendolkar <amit.tendolkar@in.ibm.com>
3434
// *HWP Team : PM
3535
// *HWP Consumed by : HB:PERV
36-
// *HWP Level : 2
36+
// *HWP Level : 3
3737

3838
//------------------------------------------------------------------------------
3939
// Includes
@@ -43,7 +43,8 @@
4343
#include <p9_quad_scom_addresses.H>
4444
#include <p9_hcd_common.H>
4545
#include <p9_common_clk_ctrl_state.H>
46-
#include "p9_hcd_l2_stopclocks.H"
46+
#include <p9_hcd_l2_stopclocks.H>
47+
#include <p9_quad_scom_addresses_fld.H>
4748

4849
//------------------------------------------------------------------------------
4950
// Constant Definitions
@@ -104,7 +105,7 @@ p9_hcd_l2_stopclocks(
104105
FAPI_DBG("Check PM_RESET_STATE_INDICATOR via GPMMR[15]");
105106
FAPI_TRY(getScom(i_target, EQ_PPM_GPMMR_SCOM, l_data64));
106107

107-
if (!l_data64.getBit<15>())
108+
if (!l_data64.getBit<EQ_PPM_GPMMR_RESET_STATE_INDICATOR>())
108109
{
109110
FAPI_DBG("Gracefully turn off power management, if fail, continue anyways");
110111
/// @todo RTC158181 suspend_pm()
@@ -125,7 +126,8 @@ p9_hcd_l2_stopclocks(
125126
FAPI_DBG("Check PERV fence status for access to CME via CPLT_CTRL1[4]");
126127
FAPI_TRY(getScom(i_target, EQ_CPLT_CTRL1, l_temp64));
127128

128-
if (l_data64.getBit<4>() == 0 && l_temp64.getBit<4>() == 0)
129+
if (!l_data64.getBit<EQ_CLOCK_STAT_SL_STATUS_PERV>() &&
130+
!l_temp64.getBit<EQ_CPLT_CTRL1_TC_PERV_REGION_FENCE>())
129131
{
130132
FAPI_DBG("Assert L2 pscom masks via RING_FENCE_MASK_LATCH_REG[2/3,10/11]");
131133
FAPI_TRY(putScom(i_target, EQ_RING_FENCE_MASK_LATCH_REG, l_l2mask_pscom));
@@ -154,17 +156,22 @@ p9_hcd_l2_stopclocks(
154156

155157
FAPI_TRY(getScom(i_target, EQ_CPLT_STAT0, l_data64));
156158
}
157-
while((l_data64.getBit<8>() != 1) && ((--l_loops1ms) != 0));
159+
while((!l_data64.getBit<EQ_CPLT_STAT0_CC_CTRL_OPCG_DONE_DC>()) &&
160+
((--l_loops1ms) != 0));
158161

159162
FAPI_ASSERT((l_loops1ms != 0),
160-
fapi2::PMPROC_L2CLKSTOP_TIMEOUT().set_EQCPLTSTAT(l_data64),
163+
fapi2::PMPROC_L2CLKSTOP_TIMEOUT()
164+
.set_TARGET(i_target)
165+
.set_EQCPLTSTAT(l_data64),
161166
"L2 Clock Stop Timeout");
162167

163168
FAPI_DBG("Check L2 clocks stopped");
164169
FAPI_TRY(getScom(i_target, EQ_CLOCK_STAT_SL, l_data64));
165170

166171
FAPI_ASSERT((((~l_data64) & l_region_clock) == 0),
167-
fapi2::PMPROC_L2CLKSTOP_FAILED().set_EQCLKSTAT(l_data64),
172+
fapi2::PMPROC_L2CLKSTOP_FAILED()
173+
.set_TARGET(i_target)
174+
.set_EQCLKSTAT(l_data64),
168175
"L2 Clock Stop Failed");
169176
FAPI_DBG("L2 clocks stopped now");
170177

@@ -188,7 +195,9 @@ p9_hcd_l2_stopclocks(
188195
while(((l_data64 & l_l2sync_clock)) && ((--l_loops1ms) != 0));
189196

190197
FAPI_ASSERT((l_loops1ms != 0),
191-
fapi2::PMPROC_CACHECLKSYNCDROP_TIMEOUT().set_EQPPMQACSR(l_data64),
198+
fapi2::PMPROC_L2CLKSYNCDROP_TIMEOUT()
199+
.set_TARGET(i_target)
200+
.set_EQPPMQACSR(l_data64),
192201
"L2 Clock Sync Drop Timeout");
193202
FAPI_DBG("L2 clock sync dones dropped");
194203

@@ -212,4 +221,3 @@ fapi_try_exit:
212221
FAPI_INF("<<p9_hcd_l2_stopclocks");
213222
return fapi2::current_err;
214223
}
215-

‎src/import/chips/p9/procedures/hwp/cache/p9_hcd_l2_stopclocks.H

+2-3
Original file line numberDiff line numberDiff line change
@@ -29,10 +29,9 @@
2929

3030
// *HWP HWP Owner : David Du <[email protected]>
3131
// *HWP Backup HWP Owner : Greg Still <[email protected]>
32-
// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com>
32+
// *HWP FW Owner : Amit Tendolkar <amit.tendolkar@in.ibm.com>
3333
// *HWP Team : PM
3434
// *HWP Consumed by : HB:PERV
35-
// *HWP Level : 2
3635

3736
#ifndef __P9_HCD_L2_STOPCLOCKS_H__
3837
#define __P9_HCD_L2_STOPCLOCKS_H__
@@ -49,7 +48,7 @@ extern "C"
4948
{
5049

5150
/// @brief Quad Clock Stop
52-
/// @param [in] i_target TARGET_TYPE_EQ target
51+
/// @param[in] i_target TARGET_TYPE_EQ target
5352
/// @return FAPI2_RC_SUCCESS if success, else error code
5453
fapi2::ReturnCode
5554
p9_hcd_l2_stopclocks(

‎src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_stopclocks_errors.xml

+81-1
Original file line numberDiff line numberDiff line change
@@ -38,26 +38,106 @@
3838
<description>
3939
cache clock stop failed.
4040
</description>
41+
<ffdc>TARGET</ffdc>
4142
<ffdc>EQCLKSTAT</ffdc>
43+
<callout>
44+
<target>TARGET</target>
45+
<priority>HIGH</priority>
46+
</callout>
47+
<callout>
48+
<procedure>CODE</procedure>
49+
<priority>LOW</priority>
50+
</callout>
51+
<deconfigure>
52+
<target>TARGET</target>
53+
</deconfigure>
54+
<deconfigure>
55+
<childTargets>
56+
<parent>TARGET</parent>
57+
<childType>TARGET_TYPE_CORE</childType>
58+
</childTargets>
59+
</deconfigure>
60+
<gard>
61+
<target>TARGET</target>
62+
</gard>
63+
<gard>
64+
<childTargets>
65+
<parent>TARGET</parent>
66+
<childType>TARGET_TYPE_CORE</childType>
67+
</childTargets>
68+
</gard>
4269
</hwpError>
4370
<!-- ********************************************************************* -->
4471
<hwpError>
4572
<rc>RC_PMPROC_CACHECLKSTOP_TIMEOUT</rc>
4673
<description>
4774
cache clock stop timed out.
4875
</description>
76+
<ffdc>TARGET</ffdc>
4977
<ffdc>EQCPLTSTAT</ffdc>
78+
<callout>
79+
<target>TARGET</target>
80+
<priority>HIGH</priority>
81+
</callout>
82+
<callout>
83+
<procedure>CODE</procedure>
84+
<priority>LOW</priority>
85+
</callout>
86+
<deconfigure>
87+
<target>TARGET</target>
88+
</deconfigure>
89+
<deconfigure>
90+
<childTargets>
91+
<parent>TARGET</parent>
92+
<childType>TARGET_TYPE_CORE</childType>
93+
</childTargets>
94+
</deconfigure>
95+
<gard>
96+
<target>TARGET</target>
97+
</gard>
98+
<gard>
99+
<childTargets>
100+
<parent>TARGET</parent>
101+
<childType>TARGET_TYPE_CORE</childType>
102+
</childTargets>
103+
</gard>
50104
</hwpError>
51105
<!-- ********************************************************************* -->
52106
<hwpError>
53107
<rc>RC_QPPM_QCCR_PB_PURGE_DONE_LVL_TIMEOUT</rc>
54108
<description>
55-
A timeout occured while waiting for Acknowledgement from
109+
A timeout occured while waiting for Acknowledgement from
56110
Powerbus that the buffers are empty and can safely be
57111
fenced and clocked off
58112
</description>
59113
<ffdc>TARGET</ffdc>
60114
<ffdc>EQPPMQCCR</ffdc>
115+
<callout>
116+
<target>TARGET</target>
117+
<priority>HIGH</priority>
118+
</callout>
119+
<callout>
120+
<procedure>CODE</procedure>
121+
<priority>LOW</priority>
122+
</callout>
123+
<deconfigure>
124+
<target>TARGET</target>
125+
</deconfigure>
126+
<deconfigure>
127+
<childTargets>
128+
<parent>TARGET</parent>
129+
<childType>TARGET_TYPE_CORE</childType>
130+
</childTargets>
131+
</deconfigure>
132+
<gard>
133+
<target>TARGET</target>
134+
</gard>
135+
<gard>
136+
<childTargets>
137+
<parent>TARGET</parent>
138+
<childType>TARGET_TYPE_CORE</childType>
139+
</childTargets>
140+
</gard>
61141
</hwpError>
62142
<!-- ********************************************************************* -->
63143
</hwpErrors>

0 commit comments

Comments
 (0)