Figure out how to hook this PHY together with LiteDRAM

[mithro]

LiteDRAM is a popular, FPGA targeted memory controller IP that Antmicro recently added LPDDR4 (and soon LPDDR5) support to ChromeOS's RowHammer experiments. See for example;

• https://antmicro.com/blog/2021/04/lpddr4-test-platform/
• https://litex-rowhammer-tester.readthedocs.io/en/latest/
• https://security.googleblog.com/2021/05/introducing-half-double-new-hammering.html

As this is the first time LiteDRAM has attempted to be used with an ASIC PHY rather than an FPGA this work will probably require a bunch of experiments. I have created an issue on the LiteDRAM issue tracker to track the work there too.