From e3ebd560a1acd3a33ab89812fa05b8257d2ee492 Mon Sep 17 00:00:00 2001
From: ptitSeb <sebastien.chev@gmail.com>
Date: Tue, 7 Mar 2023 10:22:12 +0100
Subject: [PATCH] [SINGLEPASS] Add more ROR emitter to ARM64 backend (for
 #3647)

---
 lib/compiler-singlepass/src/emitter_arm64.rs | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/lib/compiler-singlepass/src/emitter_arm64.rs b/lib/compiler-singlepass/src/emitter_arm64.rs
index 948fe793ced..aa5ee80f2c6 100644
--- a/lib/compiler-singlepass/src/emitter_arm64.rs
+++ b/lib/compiler-singlepass/src/emitter_arm64.rs
@@ -1954,6 +1954,16 @@ impl EmitterARM64 for Assembler {
                 }
                 dynasm!(self ; ror X(dst), X(src1), imm);
             }
+            (Size::S64, Location::GPR(src1), Location::Imm64(imm), Location::GPR(dst))
+            | (Size::S64, Location::Imm64(imm), Location::GPR(src1), Location::GPR(dst)) => {
+                let src1 = src1.into_index() as u32;
+                let imm = imm as u32;
+                let dst = dst.into_index() as u32;
+                if imm == 0 || imm > 63 {
+                    codegen_error!("singlepass ROR with incompatible imm {}", imm);
+                }
+                dynasm!(self ; ror X(dst), X(src1), imm);
+            }
             (Size::S32, Location::GPR(src1), Location::Imm32(imm), Location::GPR(dst))
             | (Size::S32, Location::Imm32(imm), Location::GPR(src1), Location::GPR(dst)) => {
                 let src1 = src1.into_index() as u32;