DeepSeekv4 ROCm Optimization#41601
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Code Review
This pull request enables ROCm support for DeepSeek-V4 by introducing ROCm-specific kernels and PyTorch fallbacks for attention and MoE operations. Key changes include the integration of the AITER backend, specialized handling for the e8m0 FP8 format, and ROCm-compatible Triton kernels. The review feedback correctly identifies a broadcasting error in the MQA logits fallback, hardcoded device strings that should be generalized, and an incorrect type conversion for exponent-only scales in the blocked K-cache dequantization logic.
| out_logits = torch.full( | ||
| [batch_size * next_n, max_model_len], | ||
| float("-inf"), | ||
| device="cuda", |
| out_qk = torch.full( | ||
| (heads, batch_size * next_n, max_model_len), | ||
| float("-inf"), | ||
| device="cuda", |
| cur_nope = input_nope[ | ||
| ..., tile_idx * tile_size : (tile_idx + 1) * tile_size | ||
| ].to(torch.bfloat16) | ||
| cur_scales = input_scale[:, :, tile_idx].to(torch.bfloat16).unsqueeze(-1) |
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The input_scale tensor contains float8_e8m0fnu values, which are exponent-only scales. Directly casting them to bfloat16 using .to() will not correctly decode the exponent bias. You should use the _decode_e8m0_scales helper defined in this file to perform the correct conversion.
| cur_scales = input_scale[:, :, tile_idx].to(torch.bfloat16).unsqueeze(-1) | |
| cur_scales = _decode_e8m0_scales(input_scale[:, :, tile_idx]).to(torch.bfloat16).unsqueeze(-1) |
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@bobofang11235 I noticed there are also changes to support fnuz. Please also disclose the testing results (accuracy and performance) of fnuz. Since this is an optimization PR, can you highlight what has been optimized? E2E performance before the PR and after the PR? (if the model is too slow to run to show e2e perf, please highlight what is optimized and how much gain are we getting from the highlighted optimization) |
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Hi @bobofang11235 Since the base PR #40871 has been merged, can you help update the test results with the official docker vllm/vllm-open-rocm:nightly? |
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Hi @tjtanaa,I tested the e2e accuracy, and the result is same as PR#40871 And the optimized part:
Hi @wuhuikx |
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Hi @tjtanaa client command before this PR after this PR |
Decode UE8M0 scale tensors before using them in ROCm fallback paths so E8M0 scales are not multiplied directly as float8 tensors. Use the current platform FP8 dtype for DeepSeek-V4 indexer and inverse-RoPE quantization, and select the Triton FNUZ FP8 type when required by the ROCm platform. Signed-off-by: bobofang11235 <bobo.fang@amd.com>
Route DeepSeek-V4 sparse FlashMLA prefill and decode calls through ROCm fallback implementations so ROCm can share the same FlashMLA API path as CUDA. Signed-off-by: bobofang11235 <bobo.fang@amd.com>
Wrap shuffled AITER MXFP4 weights as fresh Parameters so FP4 dtype metadata is preserved without changing non-ROCm MoE backend routing. Signed-off-by: bobofang11235 <bobo.fang@amd.com>
…s are -inf When both prefix and suffix have no tokens (e.g. chunked prefill with zero context length), both LSEs are -inf. IEEE 754: -inf - (-inf) = NaN, which propagates through exp and division into the output. Apply a branchless safe-softmax fix in the Triton kernel: - Clamp max_lse to a finite floor (-1e30) so the subtraction yields -inf instead of NaN, and exp() gives exactly 0. - Add epsilon (1e-10) to the denominator to prevent 0/0. The CUDA merge_attn_states kernel already handles this via an early-return branch on isinf(max_lse). This brings the Triton kernel to parity using an arithmetic-only approach. Add regression test covering the both-LSE-negative-inf edge case that the existing test explicitly excluded. Signed-off-by: MHYang <meng-hsuan.yang@amd.com>
Signed-off-by: MHYang <meng-hsuan.yang@amd.com>
Signed-off-by: MHYang <meng-hsuan.yang@amd.com>
Provide a ROCm-only torch fallback for fp8_einsum when DeepGEMM is unavailable while preserving the existing CUDA and non-ROCm dispatch behavior. Signed-off-by: bobofang11235 <bobo.fang@amd.com>
Signed-off-by: bobofang11235 <bobo.fang@amd.com>
Signed-off-by: bobofang11235 <bobo.fang@amd.com>
Signed-off-by: bobofang11235 <bobo.fang@amd.com>
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| _LAYER_TYPE_C128A: None, | ||
| } | ||
| if num_decode_tokens == 0 or current_platform.is_rocm(): | ||
| if num_decode_tokens == 0: |
| ) | ||
| flash_mla_sparse_fwd( | ||
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| output_chunk, _, _ = flash_mla_sparse_fwd( |
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We need to rethink this. This changes also reflects on CUDA code path
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This pull request has merge conflicts that must be resolved before it can be |
Purpose
Decode UE8M0 scale tensors before using them in ROCm fallback paths so E8M0 scales are not multiplied directly as float8 tensors. Use the current platform FP8 dtype for DeepSeek-V4 indexer and inverse-RoPE quantization,
and select the Triton FNUZ FP8 type when required by the ROCm platform.
Route DeepSeek-V4 sparse FlashMLA prefill and decode calls through ROCm fallback implementations so ROCm can share the same FlashMLA API path as CUDA.
Wrap shuffled AITER MXFP4 weights as fresh Parameters so FP4 dtype metadata is preserved without changing non-ROCm MoE backend routing.
Fix NaN output in the Triton merge_attn_states kernel when both prefix_lse and suffix_lse are -inf.
When both prefix and suffix have no tokens (e.g. chunked prefill with zero context length), both LSEs are -inf. Per IEEE 754, -inf - (-inf) = NaN, which propagates through exp and division into the final output.
Provide a ROCm-only torch fallback for fp8_einsum when DeepGEMM is unavailable while preserving the existing CUDA and non-ROCm dispatch behavior.
( this PR is based on 920bf3e of upstream )
Test Plan
Test Result
docker image: docker pull rocm/vllm-dev:deepseek-v4-mi35x
machine: mi355x
aiter version: d2454ad18a0d7c7795162ab0f550e8a0397840bd ( https://github.com/ROCm/aiter main branch )
vllm version: this PR
server command
client command
Result
accuracy command
Result
Essential Elements of an Effective PR Description Checklist
supported_models.mdandexamplesfor a new model.