Optimize syntax according to file extension

[vhda]

Consider the possibility of only loading SystemVerilog syntax when the buffer's file name extension is .sv, .svi, .svh or .svp. Do the same for Verilog AMS using the relevant extensions.

While this should improve the syntax performance, it does so at the cost of making the code much more complex. It would also make sense to include a global variable to control this behaviour, adding more complexity to the code that can eventually negate this performance improvement.

Check #147 for more information.