diff --git a/llvm/lib/Target/M68k/M68kISelLowering.cpp b/llvm/lib/Target/M68k/M68kISelLowering.cpp index 0ee3a07e15f4..c37ec304bf19 100644 --- a/llvm/lib/Target/M68k/M68kISelLowering.cpp +++ b/llvm/lib/Target/M68k/M68kISelLowering.cpp @@ -1058,6 +1058,14 @@ SDValue M68kTargetLowering::LowerFormalArguments( // Return Value Calling Convention Implementation //===----------------------------------------------------------------------===// +bool M68kTargetLowering::CanLowerReturn( + CallingConv::ID CCID, MachineFunction &MF, bool IsVarArg, + const SmallVectorImpl &Outs, LLVMContext &Context) const { + SmallVector RVLocs; + CCState CCInfo(CCID, IsVarArg, MF, RVLocs, Context); + return CCInfo.CheckReturn(Outs, RetCC_M68k); +} + SDValue M68kTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CCID, bool IsVarArg, diff --git a/llvm/lib/Target/M68k/M68kISelLowering.h b/llvm/lib/Target/M68k/M68kISelLowering.h index f9037e7ff497..d43160fe48d2 100644 --- a/llvm/lib/Target/M68k/M68kISelLowering.h +++ b/llvm/lib/Target/M68k/M68kISelLowering.h @@ -257,6 +257,11 @@ class M68kTargetLowering : public TargetLowering { SDValue LowerCall(CallLoweringInfo &CLI, SmallVectorImpl &InVals) const override; + bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, + bool isVarArg, + const SmallVectorImpl &Outs, + LLVMContext &Context) const override; + /// Lower the result values of a call into the /// appropriate copies out of appropriate physical registers. SDValue LowerReturn(SDValue Chain, CallingConv::ID CCID, bool IsVarArg, diff --git a/llvm/test/CodeGen/M68k/multiple-return.ll b/llvm/test/CodeGen/M68k/multiple-return.ll new file mode 100644 index 000000000000..f52f422b194f --- /dev/null +++ b/llvm/test/CodeGen/M68k/multiple-return.ll @@ -0,0 +1,20 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=m68k-linux -verify-machineinstrs | FileCheck %s + +define { i32, i32, i32, i32 } @test() { +; CHECK-LABEL: test: +; CHECK: .cfi_startproc +; CHECK-NEXT: ; %bb.0: ; %start +; CHECK-NEXT: move.l (4,%sp), %a0 +; CHECK-NEXT: move.l #23, (12,%a0) +; CHECK-NEXT: move.l #19, (8,%a0) +; CHECK-NEXT: move.l #17, (4,%a0) +; CHECK-NEXT: move.l #13, (%a0) +; CHECK-NEXT: move.l %a0, %d0 +; CHECK-NEXT: move.l (%sp), %a1 +; CHECK-NEXT: adda.l #4, %sp +; CHECK-NEXT: move.l %a1, (%sp) +; CHECK-NEXT: rts +start: + ret { i32, i32, i32, i32 } { i32 13, i32 17, i32 19, i32 23 } +}