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Será un simulador de cache cuyo objetivo será actuar como si de una caché de un ordenador se tratará (atendiendo peticiones de memoria del procesador, y gestionando las líneas presentes en la cache, calcular la tasa de fallos, ...)
This cache simulator is used in order to simulate substitutions in cache using replacement policies (FIFO and LRU) and write back into the cache (using the write-allocate policy).
This C project is a cache simulation of a CPU containing L1D, L1I and L2 caches. It takes an image of memory and a memory trace as input, simulates the hit/miss behavior of a cache memory on this trace, and outputs the total number of hits, misses and evictions for each cache type along with the content of each cache at the end.