SST Architectural Simulation Components and Libraries
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Updated
Jul 2, 2024 - C++
SST Architectural Simulation Components and Libraries
A low-latency LRU approximation cache in C++ using CLOCK second-chance algorithm. Multi level cache too. Up to 2.5 billion lookups per second.
A C++11 simulator for a variety of CDN caching policies.
Haystack is an analytical cache model that given a program computes the number of cache misses.
A cache simulator, using the C++ language, to simulate a direct-mapped, fully associative and set-associative cache. It has a set of memory reference generators to generate different sequences of references.
A graphics tracing and replay framework to explore system-level effects on heterogeneous CPU+GPU memory systems.
Contains implementations of cache-optimized and external memory algorithms.
Computer architecture related projects
Direct Mapped and N-Way set associative cache Simulator in C/C++ for L1 cache in Processors
A 3-level cache simulator for SPEC traces with various inclusion and block replacement policies
PKU computer organization and architecture memory hierarchy simulator LAB
An in-depth project focusing on the design and simulation of a split L1 cache in C++. This repository covers MESI protocol operations, comprehensive test cases, and simulation results, showcasing strategies for enhancing cache coherence and performance. This is a class project from ECE 585: Microprocessor System Design at Portland State University
Simulator for Direct, Associative, Set Associative Mapping Technique in Cache Allocation
Design and simulate a NAND flash memory based main memory system
The following program here helps in simulating how blocks from main memory can get mapped to cache based on strategies: Direct-Mapping, Fully-Associative, Set-Associative
RISC-V Cache and Instruction Encoding Simulation
A C++ based Cache Simulator to simulate cache hits and cache misses
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