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tjarkertjarker
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‎.gitignore

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/.bsp
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/.idea
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/build
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/project
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/target
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/test_run_dir

‎Makefile

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TOP = Top
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BUILD_DIR = build
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PART = xc7a35tcpg236-1
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CONFIG_PART = xc7a35t_0
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SRCS = $(wildcard src/main/scala/*.scala) $(wildcard src/main/scala/**/*.scala)
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BLACKBOXES =
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BLACKBOXTARGETS = $(addprefix $(BUILD_DIR)/, $(BLACKBOXES))
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VIVADO_ARGS = -nojournal -log $(BUILD_DIR)/vivado.log -tempDir $(BUILD_DIR)
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TEST_FILE ?= test.txt
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K ?= 4
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all: gen synth
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gen: $(BUILD_DIR)/$(TOP).v
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synth: $(BUILD_DIR)/$(TOP).bit
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clean:
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rm -rf $(BUILD_DIR)
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$(BUILD_DIR)/$(TOP).v: $(SRCS)
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@mkdir -p $(@D)
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sbt "runMain $(TOP) --target-dir $(BUILD_DIR) --test-file $(TEST_FILE) --k $(K)"
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$(BUILD_DIR)/$(TOP).bit: $(BUILD_DIR)/$(TOP).v pinout.xdc $(BUILD_DIR)/synth.tcl
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vivado $(VIVADO_ARGS) -mode batch -source $(BUILD_DIR)/synth.tcl
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@rm -rf usage_statistics_webtalk.html usage_statistics_webtalk.xml
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download: $(BUILD_DIR)/$(TOP).bit $(BUILD_DIR)/config.tcl
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vivado $(VIVADO_ARGS) -mode batch -source $(BUILD_DIR)/config.tcl
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@rm -rf .Xil usage_statistics_webtalk.html usage_statistics_webtalk.xml webtalk.jou webtalk.log
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$(BUILD_DIR)/synth.tcl: $(BLACKBOXTARGETS) $(BUILD_DIR)/$(TOP).v
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echo "\
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read_verilog [ glob $(BUILD_DIR)/$(TOP).v $(BLACKBOXTARGETS) ]\n\
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read_xdc ./pinout.xdc\n\
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synth_design -top $(TOP) -part $(PART)\n\
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opt_design\n\
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place_design\n\
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route_design\n\
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report_timing_summary -file $(BUILD_DIR)/sta.rpt\n\
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report_utilization -file $(BUILD_DIR)/util.rpt\n\
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write_bitstream $(BUILD_DIR)/$(TOP).bit -force" > $(BUILD_DIR)/synth.tcl
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$(BUILD_DIR)/config.tcl:
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echo "\
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open_hw_manager \n\
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connect_hw_server -allow_non_jtag \n\
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open_hw_target \n\
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current_hw_device [get_hw_devices $(CONFIG_PART)] \n\
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refresh_hw_device -update_hw_probes false [lindex [get_hw_devices $(CONFIG_PART)] 0] \n\
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set_property PROBES.FILE {} [get_hw_devices $(CONFIG_PART)] \n\
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set_property FULL_PROBES.FILE {} [get_hw_devices $(CONFIG_PART)] \n\
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set_property PROGRAM.FILE {./$(BUILD_DIR)/$(TOP).bit} [get_hw_devices $(CONFIG_PART)] \n\
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program_hw_devices [get_hw_devices $(CONFIG_PART)] \n\
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refresh_hw_device [lindex [get_hw_devices $(CONFIG_PART)] 0] \n\
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close_hw_manager" > $(BUILD_DIR)/config.tcl

‎build.sbt

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scalaVersion := "2.12.13"
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scalacOptions ++= Seq(
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"-deprecation",
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"-feature",
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"-unchecked",
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"-language:reflectiveCalls",
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)
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resolvers ++= Seq(
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Resolver.sonatypeRepo("snapshots"),
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Resolver.sonatypeRepo("releases")
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)
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val chiselVersion = "3.5.0"
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addCompilerPlugin("edu.berkeley.cs" %% "chisel3-plugin" % chiselVersion cross CrossVersion.full)
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libraryDependencies += "edu.berkeley.cs" %% "chisel3" % chiselVersion
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libraryDependencies += "edu.berkeley.cs" %% "chisel-iotesters" % "2.5.0"
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libraryDependencies += "edu.berkeley.cs" %% "chiseltest" % "0.5.0"

‎pinout.xdc

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set_property IOSTANDARD LVCMOS33 [get_ports *]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property CFGBVS VCCO [current_design]
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## Clock signal
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set_property PACKAGE_PIN W5 [get_ports {clock}]
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create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clock}]
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## Switches
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#set_property PACKAGE_PIN V17 [get_ports {sw[0]}]
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#set_property PACKAGE_PIN V16 [get_ports {sw[1]}]
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#set_property PACKAGE_PIN W16 [get_ports {sw[2]}]
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#set_property PACKAGE_PIN W17 [get_ports {sw[3]}]
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#set_property PACKAGE_PIN W15 [get_ports {sw[4]}]
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#set_property PACKAGE_PIN V15 [get_ports {sw[5]}]
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#set_property PACKAGE_PIN W14 [get_ports {sw[6]}]
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#set_property PACKAGE_PIN W13 [get_ports {sw[7]}]
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#set_property PACKAGE_PIN V2 [get_ports {sw[8]}]
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#set_property PACKAGE_PIN T3 [get_ports {sw[9]}]
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#set_property PACKAGE_PIN T2 [get_ports {sw[10]}]
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#set_property PACKAGE_PIN R3 [get_ports {sw[11]}]
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#set_property PACKAGE_PIN W2 [get_ports {sw[12]}]
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#set_property PACKAGE_PIN U1 [get_ports {sw[13]}]
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#set_property PACKAGE_PIN T1 [get_ports {sw[14]}]
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#set_property PACKAGE_PIN R2 [get_ports {sw[15]}]
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## LEDs
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set_property PACKAGE_PIN U16 [get_ports {io_value[0]}]
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set_property PACKAGE_PIN E19 [get_ports {io_value[1]}]
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set_property PACKAGE_PIN U19 [get_ports {io_value[2]}]
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set_property PACKAGE_PIN V19 [get_ports {io_value[3]}]
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set_property PACKAGE_PIN W18 [get_ports {io_value[4]}]
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#set_property PACKAGE_PIN U15 [get_ports {led[5]}]
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#set_property PACKAGE_PIN U14 [get_ports {led[6]}]
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#set_property PACKAGE_PIN V14 [get_ports {led[7]}]
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#set_property PACKAGE_PIN V13 [get_ports {led[8]}]
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#set_property PACKAGE_PIN V3 [get_ports {led[9]}]
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#set_property PACKAGE_PIN W3 [get_ports {led[10]}]
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#set_property PACKAGE_PIN U3 [get_ports {led[11]}]
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#set_property PACKAGE_PIN P3 [get_ports {led[12]}]
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#set_property PACKAGE_PIN N3 [get_ports {led[13]}]
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#set_property PACKAGE_PIN P1 [get_ports {led[14]}]
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#set_property PACKAGE_PIN L1 [get_ports {led[15]}]
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##Buttons
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#set_property PACKAGE_PIN U18 [get_ports btnC]
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#set_property PACKAGE_PIN T18 [get_ports btnU]
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#set_property PACKAGE_PIN W19 [get_ports btnL]
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#set_property PACKAGE_PIN T17 [get_ports btnR]
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#set_property PACKAGE_PIN U17 [get_ports btnD]
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##7 segment display
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#set_property PACKAGE_PIN W7 [get_ports {seg[0]}]
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#set_property PACKAGE_PIN W6 [get_ports {seg[1]}]
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#set_property PACKAGE_PIN U8 [get_ports {seg[2]}]
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#set_property PACKAGE_PIN V8 [get_ports {seg[3]}]
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#set_property PACKAGE_PIN U5 [get_ports {seg[4]}]
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#set_property PACKAGE_PIN V5 [get_ports {seg[5]}]
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#set_property PACKAGE_PIN U7 [get_ports {seg[6]}]
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#set_property PACKAGE_PIN V7 [get_ports {dp}]
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#set_property PACKAGE_PIN U2 [get_ports {an[0]}]
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#set_property PACKAGE_PIN U4 [get_ports {an[1]}]
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#set_property PACKAGE_PIN V4 [get_ports {an[2]}]
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#set_property PACKAGE_PIN W4 [get_ports {an[3]}]
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##VGA Connector
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#set_property PACKAGE_PIN G19 [get_ports {vgaRed[0]}]
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#set_property PACKAGE_PIN H19 [get_ports {vgaRed[1]}]
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#set_property PACKAGE_PIN J19 [get_ports {vgaRed[2]}]
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#set_property PACKAGE_PIN N19 [get_ports {vgaRed[3]}]
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#set_property PACKAGE_PIN N18 [get_ports {vgaBlue[0]}]
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#set_property PACKAGE_PIN L18 [get_ports {vgaBlue[1]}]
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#set_property PACKAGE_PIN K18 [get_ports {vgaBlue[2]}]
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#set_property PACKAGE_PIN J18 [get_ports {vgaBlue[3]}]
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#set_property PACKAGE_PIN J17 [get_ports {vgaGreen[0]}]
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#set_property PACKAGE_PIN H17 [get_ports {vgaGreen[1]}]
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#set_property PACKAGE_PIN G17 [get_ports {vgaGreen[2]}]
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#set_property PACKAGE_PIN D17 [get_ports {vgaGreen[3]}]
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#set_property PACKAGE_PIN P19 [get_ports {Hsync}]
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#set_property PACKAGE_PIN R19 [get_ports {Vsync}]
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##USB-RS232 Interface
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#set_property PACKAGE_PIN B18 [get_ports {RsRx}]
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#set_property PACKAGE_PIN A18 [get_ports {RsTx}]
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##USB HID (PS/2)
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#set_property PACKAGE_PIN C17 [get_ports PS2Clk]
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#set_property PULLUP true [get_ports PS2Clk]
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#set_property PACKAGE_PIN B17 [get_ports PS2Data]
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#set_property PULLUP true [get_ports PS2Data]
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##Pmod Header JA
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#set_property PACKAGE_PIN J1 [get_ports {JA[0]}]
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#set_property PACKAGE_PIN L2 [get_ports {JA[1]}]
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#set_property PACKAGE_PIN J2 [get_ports {JA[2]}]
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#set_property PACKAGE_PIN G2 [get_ports {JA[3]}]
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#set_property PACKAGE_PIN H1 [get_ports {JA[4]}]
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#set_property PACKAGE_PIN K2 [get_ports {JA[5]}]
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#set_property PACKAGE_PIN H2 [get_ports {JA[6]}]
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#set_property PACKAGE_PIN G3 [get_ports {JA[7]}]
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##Pmod Header JB
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set_property PACKAGE_PIN A14 [get_ports {io_go}]
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set_property PACKAGE_PIN A16 [get_ports {reset}]
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#set_property PACKAGE_PIN B15 [get_ports {JB[2]}]
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#set_property PACKAGE_PIN B16 [get_ports {JB[3]}]
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#set_property PACKAGE_PIN A15 [get_ports {JB[4]}]
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#set_property PACKAGE_PIN A17 [get_ports {JB[5]}]
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#set_property PACKAGE_PIN C15 [get_ports {JB[6]}]
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#set_property PACKAGE_PIN C16 [get_ports {JB[7]}]
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##Pmod Header JC
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#set_property PACKAGE_PIN K17 [get_ports {JC[0]}]
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#set_property PACKAGE_PIN M18 [get_ports {JC[1]}]
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#set_property PACKAGE_PIN N17 [get_ports {JC[2]}]
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#set_property PACKAGE_PIN P18 [get_ports {JC[3]}]
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#set_property PACKAGE_PIN L17 [get_ports {JC[4]}]
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#set_property PACKAGE_PIN M19 [get_ports {JC[5]}]
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#set_property PACKAGE_PIN P17 [get_ports {JC[6]}]
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#set_property PACKAGE_PIN R18 [get_ports {JC[7]}]

‎src/main/scala/HeapSorter.scala

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import chisel3._
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class HeapSorter extends Module {
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val io = IO(new Bundle {
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})
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}

‎src/main/scala/Heapifier.scala

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import Types.MemoryIO
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import chisel3._
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import chisel3.experimental.ChiselEnum
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import chisel3.util._
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import Heapifier.State
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object Heapifier {
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object State extends ChiselEnum {
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val Idle, ReceiveParent, ReceiveLeftChild, ReceiveRightChildAndCompare, RequestLeftChild = Value
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}
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}
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class Heapifier(heapSize: Int) extends Module {
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val io = IO(new Bundle {
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val memory = Flipped(new MemoryIO)
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val request = Flipped(Decoupled(new Bundle {
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val index = UInt(log2Ceil(heapSize).W)
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}))
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})
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io.memory := 0.U.asTypeOf(io.memory)
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def leftChildIndex(x: UInt): UInt = (x << 1).asUInt
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def rightChildIndex(x: UInt): UInt = (x << 1).asUInt + 1.U
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val stateReg = RegInit(State.Idle)
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val indexReg = Reg(UInt(log2Ceil(heapSize).W))
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val parentReg = Reg(UInt(32.W))
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val leftChildReg = Reg(UInt(32.W))
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val rightChild = WireDefault(io.memory.readValue)
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val captureLargest = WireDefault(0.B)
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val largest = RegEnable(Max(leftChildReg, rightChild, parentReg), captureLargest)
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val largestIsParent = largest.index === 0.U
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val nextParent = indexReg + largest.index
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switch(stateReg) {
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is(State.Idle) {
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io.request.ready := 1.B
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indexReg := io.request.bits.index
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io.memory.readAddress := io.request.bits.index
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when(io.request.valid) {
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stateReg := State.ReceiveParent
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}
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}
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is(State.ReceiveParent) {
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parentReg := io.memory.readValue
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io.memory.readAddress := leftChildIndex(indexReg)
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stateReg := State.ReceiveLeftChild
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}
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is(State.ReceiveLeftChild) {
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leftChildReg := io.memory.readValue
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io.memory.readAddress := rightChildIndex(indexReg)
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stateReg := State.ReceiveRightChildAndCompare
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}
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is(State.ReceiveRightChildAndCompare) {
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captureLargest := 1.B
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stateReg := State.RequestLeftChild
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}
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is(State.RequestLeftChild) {
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io.memory.writeAddress := indexReg
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io.memory.writeValue := largest.item
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io.memory.writeEnable := !largestIsParent
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io.memory.readAddress := leftChildIndex(nextParent)
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indexReg := nextParent
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parentReg := largest.item
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stateReg := Mux(largestIsParent, State.Idle, State.ReceiveLeftChild)
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}
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}
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}

‎src/main/scala/Max.scala

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import chisel3._
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object Max {
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object Indexed {
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def fromTuple(init: (UInt,Int)): Indexed = {
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val w = Wire(new Indexed)
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w.item := init._1
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w.index := init._2.U
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w
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}
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}
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class Indexed extends Bundle {
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val item = UInt(32.W)
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val index = UInt()
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}
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def apply(values: UInt*): Indexed =
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VecInit(values.zipWithIndex.map(Indexed.fromTuple)).reduceTree { (left,right) =>
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Mux(left.item > right.item, left, right)
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}
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}

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