memdec.gal

GAL22V10
MEMDEC

CLK /RFSH     M1       NC      /MREQ    /RD     XRAMEN ROMEN A13     A14     A15    GND
NC  /CRTESEL /CRTCSEL /CRTASEL /CRT8SEL  XRAMAD NC     NC    M1WAIT /RAMSEL /ROMSEL VCC

;
; This implements memory space decoding and M1 wait-state generation for
; the CoPicoVision.
;

;
; The ColecoVision has the following memory space address map:
;
; $0000 - BIOS ROM
; $2000 - Expansion
; $4000 - Expansion
; $6000 - RAM
; $8000 - Cartridge selector 0
; $A000 - Cartridge selector 1
; $C000 - Cartridge selector 2
; $E000 - Cartridge selector 3
;
; The Super Game Module adds extended RAM and the ability to disable the
; BIOS ROM.  These are controlled by the XRAMEN and ROMEN inputs.
;
; If the CPU is performing a DRAM refresh, no addresses are decoded.
; 
ROMSEL   = /A15 * /A14 * /A13 * MREQ * /RFSH *  RD *  ROMEN ; ROM (en) reads

RAMSEL   = /A15 * /A14 * /A13 * MREQ * /RFSH *  RD * /ROMEN ; ROM (dis) reads
         + /A15 * /A14 * /A13 * MREQ * /RFSH * /RD          ; ROM writes
         + /A15 * /A14 *  A13 * MREQ * /RFSH * XRAMEN       ; XRAM $2000
         + /A15 *  A14 * /A13 * MREQ * /RFSH * XRAMEN       ; XRAM $4000
         + /A15 *  A14 *  A13 * MREQ * /RFSH                ; base RAM $6000

;
; A10-A12 need to be valid on the RAM address bus UNLESS we're accessing
; the base RAM page with XRAMEN disabled.  XRAMAD provides the signal
; that facilitates this to a 74HCT08 that gates those address lines.
; XRAMAD is an active-high output, but we negate it here so that it's
; high whenever these conditions are NOT true.
;
/XRAMAD  = /A15 *  A14 *  A13 * MREQ * /RFSH * /XRAMEN      ; base RAM $6000

CRT8SEL  =  A15 * /A14 * /A13 * MREQ * /RFSH
CRTASEL  =  A15 * /A14 *  A13 * MREQ * /RFSH
CRTCSEL  =  A15 *  A14 * /A13 * MREQ * /RFSH
CRTESEL  =  A15 *  A14 *  A13 * MREQ * /RFSH

;
; M1 wait-state generation.
;
; According to the Z80 manual, M1 starts nominally high, which asserts
; the async-reset on the OLMC flip-flops, thus driving our M1WAIT output
; low.
;
; When the M1 machine cycle starts, our M1 input goes low, thus de-asserting
; our async-reset.  Then, when CLK goes high at the start of M1T2, we latch
; the inverse of our M1WAIT output into the M1WAIT flip-flop, thus driving
; our M1WAIT output high.  M1WAIT is externally connected to an open-drain
; inverter to assert the wired-OR /WAIT input on the Z80.  When the Z80
; samples /WAIT at the falling edge of CLK in the middle of M1T2, the Z80
; will enter wait-state.
;
; On the next rising edge of CLK in our elgongated M1T2, the inverse of the
; M1WAIT output will again be latched into the M1WAIT flip-flop, thus driving
; our M1WAIT output low, which in turn will de-assert /WAIT on the Z80.  At
; the next falling edge of CLK, the Z80 will again sample /WAIT and find it
; de-asserted and continue on with M1T2.
;
; The M1 input will continue to be low until just after the rising edge of
; CLK that marks the beginning of M1T3.  However, M1 will go high, and thus
; assert the async-reset of the M1WAIT flip-flop, thus ensuring that we will
; not re-assert /WAIT, before the next falling edge of CLK.
;
; The net effect is that M1T2 is extended for one clock cycle in order to
; meet the requirements of any slow memory that might participate in opcode
; fetch.  This is not needed for other memory read or write cycles because
; the access times are a fair bit longer in those scenarios.
;
AR = M1
M1WAIT.R = /M1WAIT

DESCRIPTION

This is the memory address decoder and M1 wait-state generator for the
CoPicoVision.