From 02a1bb708ca12d5d9eb51ac00e57722d8b5e6844 Mon Sep 17 00:00:00 2001 From: "Tadashi G. Takaoka" Date: Tue, 9 Apr 2024 13:43:49 +0900 Subject: [PATCH] [P8085] Read control signals as bus Assign control signals, S0, S1, #RD, #WR and #INTA to P9 and read those signals at once. --- debugger/i8085/devs_i8085.cpp | 4 + debugger/i8085/devs_i8085.h | 1 + debugger/i8085/inst_i8085.h | 10 +- debugger/i8085/pins_i8085.cpp | 297 +- debugger/i8085/pins_i8085.h | 40 +- debugger/i8085/signals_i8085.cpp | 25 +- debugger/i8085/signals_i8085.h | 18 +- samples/i8085/echo.asm | 4 + samples/i8085/echo.hex | 5 +- samples/i8085/echo.lst | 82 +- samples/i8085/echoir.asm | 1 + samples/i8085/echoir.hex | 17 +- samples/i8085/echoir.lst | 367 +- samples/i8085/sio.asm | 4 + samples/i8085/sio.hex | 11 +- samples/i8085/sio.lst | 214 +- schematics/p8085/0-LocalLibrary.kicad_sym | 746 ++- .../Bionic-P135_Vertical.kicad_mod | 77 + .../Bionic-P245_Vertical.kicad_mod | 77 + .../DIP-40_W15.24mm_Socket.kicad_mod | 115 + .../0-LocalLibrary/DIP-48_W7.62mm.kicad_mod | 87 - .../LED_CSL1901UW1_ROM.kicad_mod | 90 + .../0-LocalLibrary/SOT-23_MC_MCH-M.kicad_mod | 93 + schematics/p8085/bionic-p8085.kicad_pcb | 5617 +++++++++++++++-- schematics/p8085/bionic-p8085.kicad_prl | 5 +- schematics/p8085/bionic-p8085.kicad_pro | 4 +- schematics/p8085/bionic-p8085.kicad_sch | 1906 ++++-- schematics/p8085/bionic-p8085.pdf | Bin 66623 -> 69890 bytes schematics/p8085/mezzanine_pin.txt | 14 +- schematics/p8085/p8085ah_bionic.toml | 18 +- 30 files changed, 7783 insertions(+), 2166 deletions(-) create mode 100644 schematics/p8085/0-LocalLibrary/Bionic-P135_Vertical.kicad_mod create mode 100644 schematics/p8085/0-LocalLibrary/Bionic-P245_Vertical.kicad_mod create mode 100644 schematics/p8085/0-LocalLibrary/DIP-40_W15.24mm_Socket.kicad_mod delete mode 100644 schematics/p8085/0-LocalLibrary/DIP-48_W7.62mm.kicad_mod create mode 100644 schematics/p8085/0-LocalLibrary/LED_CSL1901UW1_ROM.kicad_mod create mode 100644 schematics/p8085/0-LocalLibrary/SOT-23_MC_MCH-M.kicad_mod diff --git a/debugger/i8085/devs_i8085.cpp b/debugger/i8085/devs_i8085.cpp index 0efe534a..864def07 100644 --- a/debugger/i8085/devs_i8085.cpp +++ b/debugger/i8085/devs_i8085.cpp @@ -37,6 +37,10 @@ void DevsI8085::write(uint32_t addr, uint16_t data) const { USART.write(addr, data); } +uint16_t DevsI8085::vector() const { + return USART.vector(); +} + Device &DevsI8085::parseDevice(const char *name) const { if (strcasecmp(name, USART.name()) == 0) return USART; diff --git a/debugger/i8085/devs_i8085.h b/debugger/i8085/devs_i8085.h index 47b026bd..db8db500 100644 --- a/debugger/i8085/devs_i8085.h +++ b/debugger/i8085/devs_i8085.h @@ -15,6 +15,7 @@ struct DevsI8085 final : Devs { bool isSelected(uint32_t addr) const override; uint16_t read(uint32_t addr) const override; void write(uint32_t addr, uint16_t data) const override; + uint16_t vector() const override; Device &parseDevice(const char *name) const override; void enableDevice(Device &dev) override; diff --git a/debugger/i8085/inst_i8085.h b/debugger/i8085/inst_i8085.h index 23f29456..90aac26d 100644 --- a/debugger/i8085/inst_i8085.h +++ b/debugger/i8085/inst_i8085.h @@ -8,10 +8,16 @@ namespace i8085 { struct InstI8085 { static constexpr uint8_t NOP = 0x00; - static constexpr uint8_t RST0 = 0xC7; static constexpr uint8_t HLT = 0x76; - static constexpr uint8_t EI = 0xFB; + static constexpr uint8_t RET = 0xC9; static constexpr uint8_t DI = 0xF3; + static constexpr uint8_t EI = 0xFB; + + static constexpr uint16_t ORG_TRAP = 0x0024; + static uint8_t vec2Inst(uint8_t vec) { return RST0 | (vec & 0x38); } + +private: + static constexpr uint8_t RST0 = 0xC7; }; } // namespace i8085 diff --git a/debugger/i8085/pins_i8085.cpp b/debugger/i8085/pins_i8085.cpp index 32b1581d..e31c810f 100644 --- a/debugger/i8085/pins_i8085.cpp +++ b/debugger/i8085/pins_i8085.cpp @@ -16,18 +16,20 @@ struct PinsI8085 Pins; // clang-format off /** * P8085 bus cycle. + * |----T1-----|----T2-----|----T3-----|----T1-----|----T2-----|----T3-----| + * |-T1A-|-T1B-|-T2A-|-T2B-|-T3A-|-T3B-|-T1A-|-T1B-|-T2A-|-T2B-|-T3A-|-T3B-| * __ __ __ __ __ __ __ __ __ __ __ __ __ * X1 _| |__| |__| |__| |__| |__| |__| |__| |__| |__| |__| |__| |__| | - * __ \____\ \_____\ \_____\ \_____\ \_____\ \_____\ + * _\ \____\ \_____\ \_____\ \_____\ \_____\ \_____\ * CLK |____T|1 |____T|2 |____T|3 |____T|1 |____T|2 |____T|3 |__ - * _____ \ \ _____ \ \ ___ - * ALE _| |_______|_________________|___| |_______|_________________|___| - * ___________ | _____| _____________|_________________| __ - * AD --<___________>|-----------<_____|>--<_____________X_________________>----<__ - * _______________| |_________________|_________________|_______ - * #RD |_________________| | | - * ___________________________________________________| |_______ - * #WR |_________________| + * |_____| \ | |_____| \ | ___ + * ALE __| |_______|_______________|_____| |_______|_______________|___| + * ___________ | _____| _______________|_______________| __ + * AD ---<___________>|---------<_____|>--<_______________X_______________>----<__ + * ________________| |___________________|_______________|_______ + * #RD |_______________| | | + * ____________________________________________________| |_______ + * #WR |_______________| */ // clang-format on @@ -50,15 +52,17 @@ namespace { // tCA: min 120 ns ; A8-15 valid after control // tCL: min 50 ns ; trailing control to leading ALE -constexpr auto x1_hi_ns = 64; // 80 ns -constexpr auto x1_lo_ns = 64; // 80 ns -constexpr auto clk_hi_x1_hi = 42; // 80 ns -constexpr auto clk_hi_x1_lo = 62; // 80 ns -constexpr auto clk_lo_x1_hi = 62; // 80 ns -constexpr auto clk_lo_x1_lo = 50; // 80 ns -constexpr auto t1_lo_ns = 80; -constexpr auto t2_lo_ns = 4; -constexpr auto t2_hi_ns = 2; +constexpr auto x1_hi_ns = 100; +constexpr auto x1_lo_ns = 100; +constexpr auto clk_hi_x1_lo = 44; // 80 ns +constexpr auto clk_hi_x1_hi = 60; // 80 ns +constexpr auto clk_lo_x1_lo = 60; // 80 ns +constexpr auto clk_lo_x1_hi = 60; // 80 ns +constexpr auto t1b_hi_ns = 50; // 80 ns +constexpr auto t2a_hi_ns = 58; // 80 ns +constexpr auto t2b_hi_ns = 40; // 80 ns +constexpr auto t3a_hi_capture = 25; // 80 ns; +constexpr auto t1_lo_ns = 100; inline void x1_hi() { digitalWriteFast(PIN_X1, HIGH); @@ -124,13 +128,13 @@ void assert_reset() { // Drive RESET condition x1_lo(); digitalWriteFast(PIN_RESET, LOW); - negate_hold(); - negate_trap(); - negate_intr(); - assert_ready(); digitalWriteFast(PIN_RST55, LOW); digitalWriteFast(PIN_RST65, LOW); digitalWriteFast(PIN_RST75, LOW); + negate_trap(); + negate_intr(); + negate_hold(); + assert_ready(); } void negate_reset() { @@ -180,30 +184,33 @@ const uint8_t PINS_INPUT[] = { }; inline void x1_cycle() { - x1_hi(); - delayNanoseconds(x1_hi_ns); x1_lo(); delayNanoseconds(x1_lo_ns); + x1_hi(); + delayNanoseconds(x1_hi_ns); } -inline void clk_hi() { - x1_hi(); - delayNanoseconds(clk_hi_x1_hi); - SioH.loop(); +inline void clk_hi_nowait() { x1_lo(); + delayNanoseconds(clk_lo_x1_lo); + x1_hi(); } -inline void clk_lo() { - x1_hi(); +inline void clk_hi() { + clk_hi_nowait(); delayNanoseconds(clk_lo_x1_hi); - x1_lo(); } -inline void clk_cycle() { - clk_hi(); +inline void clk_lo_nowait() { + x1_lo(); delayNanoseconds(clk_hi_x1_lo); - clk_lo(); - delayNanoseconds(clk_lo_x1_lo); + SioH.loop(); + x1_hi(); +} + +inline void clk_lo() { + clk_lo_nowait(); + delayNanoseconds(clk_hi_x1_hi); } } // namespace @@ -220,45 +227,48 @@ void PinsI8085::reset() { x1_cycle(); while (signal_clk() != LOW) x1_cycle(); + // CLK=L // #RESET_IN should be kept low for a minimum of three clock // #periods to ensure proper synchronization of the CPU. - for (auto i = 0; i < 3; i++) - clk_cycle(); + for (auto i = 0; i < 5; i++) { + clk_hi(); + clk_lo(); + } negate_reset(); // #RESET_IN is sampled here falling transition of next CLK. - clk_cycle(); cycleT1(); cycleT2Pause(); - _inta = InstI8085::NOP; Regs.save(); } Signals *PinsI8085::cycleT1() const { - auto signals = Signals::put(); - // Do T4/T5 if any, and confirm T1L by ALE=H - while (signal_ale() == LOW) - clk_cycle(); - // T1H - clk_hi(); - while (signal_ale() == HIGH) - ; - signals->getAddress(); - // T2L - clk_lo(); - return signals; + auto s = Signals::put(); + // Do T4/T5 if any, and confirm T1AL by ALE=H + // CLK=L + while (signal_ale() == LOW) { + clk_hi(); + clk_lo(); + } + // T1AL + x1_lo(); + s->getAddress(); + // T1BH + x1_hi(); + delayNanoseconds(t1b_hi_ns); + return s; } Signals *PinsI8085::cycleT2() const { - delayNanoseconds(t2_lo_ns); - auto signals = Signals::put(); - // T2H - clk_hi(); - delayNanoseconds(t2_hi_ns); - signals->getDirection(); - // T3L - clk_lo(); - return signals; + // T2A + clk_lo_nowait(); + auto s = Signals::put(); + delayNanoseconds(t2a_hi_ns); + // T2B + clk_hi_nowait(); + s->getDirection(); + delayNanoseconds(t2b_hi_ns); + return s; } Signals *PinsI8085::cycleT2Pause() const { @@ -268,55 +278,57 @@ Signals *PinsI8085::cycleT2Pause() const { Signals *PinsI8085::cycleT2Ready(uint16_t pc) const { assert_ready(); - auto signals = cycleT2(); - signals->setAddress(pc); - return signals; -} - -Signals *PinsI8085::cycleT3(Signals *signals) { - // T3L - if (signals->memory()) { // Memory access - if (signals->read()) { - if (signals->readMemory()) { - signals->data = Memory.raw_read(signals->addr); + auto s = cycleT2(); + s->setAddress(pc); + return s; +} + +Signals *PinsI8085::cycleT3(Signals *s) { + // T3A + clk_lo_nowait(); + if (s->write()) { + s->getData(); + if (s->memory()) { + if (s->writeMemory()) { + Memory.raw_write(s->addr, s->data); + } else { + delayNanoseconds(t3a_hi_capture); } - busMode(AD, OUTPUT); - busWrite(AD, signals->data); - } else if (signals->write()) { - signals->getData(); - if (signals->writeMemory()) { - Memory.raw_write(signals->addr, signals->data); + } else if (s->write()) { + const uint8_t ioaddr = s->addr; + if (Devs.isSelected(ioaddr)) { + Devs.write(ioaddr, s->data); } } - } else { // I/O access - const uint8_t ioaddr = signals->addr; - if (signals->read()) { - if (Devs.isSelected(ioaddr)) { - signals->data = Devs.read(ioaddr); - } else { - signals->data = 0; + } else { + if (s->memory()) { // Memory access + if (s->readMemory()) { + s->data = Memory.raw_read(s->addr); } - busMode(AD, OUTPUT); - busWrite(AD, signals->data); - } else if (signals->write()) { - signals->getData(); - if (Devs.isSelected(ioaddr)) { - Devs.write(ioaddr, signals->data); + } else { // I/O access + const uint8_t ioaddr = s->addr; + if (s->vector()) { + s->data = InstI8085::vec2Inst(Devs.vector()); + } else if (Devs.isSelected(ioaddr)) { + s->data = Devs.read(ioaddr); + } else { + s->data = 0; } - } else if (signals->vector()) { - signals->data = _inta; - busMode(AD, OUTPUT); - busWrite(AD, signals->data); - _inta = InstI8085::NOP; } + busWrite(AD, s->data); + busMode(AD, OUTPUT); } - // T3H - clk_hi(); + // T3B + clk_hi_nowait(); Signals::nextCycle(); busMode(AD, INPUT); - // T1L or T4L/T5L + // T1AL or T4/T5 clk_lo(); - return signals; + while (signal_ale() == LOW) { + clk_hi(); + clk_lo(); + } + return s; } void PinsI8085::execInst(const uint8_t *inst, uint8_t len) { @@ -333,19 +345,19 @@ uint8_t PinsI8085::execute(const uint8_t *inst, uint8_t len, uint16_t *addr, uint8_t inj = 0; uint8_t cap = 0; while (inj < len || cap < max) { - auto signals = (inj == 0) ? cycleT2Ready(Regs.nextIp()) : cycleT2(); + auto s = (inj == 0) ? cycleT2Ready(Regs.nextIp()) : cycleT2(); if (inj < len) - signals->inject(inst[inj]); + s->inject(inst[inj]); if (cap < max) - signals->capture(); - cycleT3(signals); - if (signals->read()) + s->capture(); + cycleT3(s); + if (s->read()) { ++inj; - if (signals->write()) { + } else if (s->write()) { if (cap == 0 && addr) - *addr = signals->addr; + *addr = s->addr; if (cap < max && buf) - buf[cap++] = signals->data; + buf[cap++] = s->data; } delayNanoseconds(t1_lo_ns); cycleT1(); @@ -360,50 +372,76 @@ void PinsI8085::idle() { } void PinsI8085::loop() { + auto s = cycleT2Ready(Regs.nextIp()); while (true) { + cycleT3(s); Devs.loop(); - const auto &s = Signals::put(); - if (!rawStep(s->addr, false) || haltSwitch()) { + if (haltSwitch()) { + suspend(); + return; + } + s = cycleT1(); + if (s->fetch() && Memory.raw_read(s->addr) == InstI8085::HLT) { cycleT2Pause(); - restoreBreakInsts(); - disassembleCycles(); - Regs.save(); return; } + cycleT2(); } } void PinsI8085::run() { Regs.restore(); Signals::resetCycles(); - rawStep(Regs.nextIp(), false); - assert_ready(); saveBreakInsts(); loop(); + restoreBreakInsts(); + disassembleCycles(); + Regs.save(); +} + +void PinsI8085::suspend() { + assert_trap(); + auto s = cycleT1(); + while (true) { + if (s->fetch() && s->addr == InstI8085::ORG_TRAP) { + negate_trap(); + s->inject(InstI8085::RET); + cycleT3(cycleT2()); + while (!cycleT1()->fetch()) { + cycleT3(cycleT2()); + } + Signals::discard(s->prev(3)); + Signals::put()->getAddress(); + cycleT2Pause(); + return; + } + cycleT3(cycleT2()); + delayNanoseconds(t1_lo_ns); + s = cycleT1(); + } } -bool PinsI8085::rawStep(uint16_t pc, bool step) { +bool PinsI8085::rawStep() { + const auto pc = Regs.nextIp(); if (Memory.raw_read(pc) == InstI8085::HLT) { cycleT2Pause(); return false; } cycleT3(cycleT2Ready(pc)); while (true) { - auto *signals = cycleT1(); - if (signals->fetch()) + if (cycleT1()->fetch()) break; cycleT3(cycleT2()); delayNanoseconds(t1_lo_ns); } - if (step) - cycleT2Pause(); + cycleT2Pause(); return true; } bool PinsI8085::step(bool show) { Regs.restore(); Signals::resetCycles(); - if (rawStep(Regs.nextIp(), true)) { + if (rawStep()) { if (show) printCycles(); Regs.save(); @@ -412,18 +450,6 @@ bool PinsI8085::step(bool show) { return false; } -uint8_t PinsI8085::intrToInta(uint8_t name) { - switch (name) { - default: - return InstI8085::RST0 | (name & 0x38); - case INTR_RST55: - case INTR_RST65: - case INTR_RST75: - case INTR_TRAP: - return InstI8085::NOP; - } -} - void PinsI8085::assertInt(uint8_t name) { switch (name) { default: @@ -438,13 +464,9 @@ void PinsI8085::assertInt(uint8_t name) { case INTR_RST75: digitalWriteFast(PIN_RST75, HIGH); break; - case INTR_TRAP: - assert_trap(); - break; case INTR_NONE: break; } - _inta = intrToInta(name); } void PinsI8085::negateInt(uint8_t name) { @@ -461,9 +483,6 @@ void PinsI8085::negateInt(uint8_t name) { case INTR_RST75: digitalWriteFast(PIN_RST75, LOW); break; - case INTR_TRAP: - negate_trap(); - break; case INTR_NONE: break; } diff --git a/debugger/i8085/pins_i8085.h b/debugger/i8085/pins_i8085.h index f32aeab9..4e36eaa3 100644 --- a/debugger/i8085/pins_i8085.h +++ b/debugger/i8085/pins_i8085.h @@ -28,26 +28,30 @@ #define PIN_RST55 10 /* P7.00 */ #define PIN_RST65 12 /* P7.01 */ #define PIN_RST75 11 /* P7.02 */ -#define PORT_S 7 /* GPIO7 */ -#define S_gp 16 /* P7.16-P7.19 */ -#define S_gm 0x3 /* P7.16-P7.19 */ -#define S_vp 0 /* S0-S1 */ -#define PIN_S0 8 /* P7.16 */ -#define PIN_S1 7 /* P7.17 */ +#define PIN_INTR 8 /* P7.16 */ +#define PIN_TRAP 7 /* P7.17 */ #define PIN_HLDA 36 /* P7.18 */ #define PIN_HOLD 37 /* P7.19 */ -#define PIN_ALE 2 /* P9.04 */ -#define PIN_INTR 4 /* P9.06 */ -#define PIN_TRAP 33 /* P9.06 */ +#define PORT_CNTL 9 /* GPIO9 */ +#define CNTL_gp 4 /* P9.04-P9.08 */ +#define CNTL_gm 0x1F /* P9.04-P9.08 */ +#define CNTL_vp 0 /* CNTL0-CNTL4 */ +#define PIN_S0 2 /* P9.04 */ +#define PIN_S1 3 /* P9.05 */ +#define PIN_RD 4 /* P9.06 */ +#define PIN_WR 33 /* P9.07 */ +#define PIN_INTA 5 /* P9.08 */ +#define CNTL_S 0x03 /* CNTL0-CNTL1 */ +#define CNTL_RD 0x04 /* CNTL2 */ +#define CNTL_WR 0x08 /* CNTL3 */ +#define CNTL_INTA 0x10 /* CNTL4 */ +#define PIN_CLK 29 /* P9.31 */ #define PIN_SOD 0 /* P6.03 */ #define PIN_SID 1 /* P6.02 */ -#define PIN_X1 5 /* P9.08 */ -#define PIN_CLK 29 /* P9.09 */ -#define PIN_RD 6 /* P7.10 */ -#define PIN_WR 9 /* P7.11 */ +#define PIN_X1 6 /* P7.10 */ #define PIN_READY 32 /* P7.12 */ #define PIN_RESET 28 /* P8.18 */ -#define PIN_INTA 31 /* P8.22 */ +#define PIN_ALE 31 /* P8.22 */ #define PIN_IOM 30 /* P8.23 */ #include "pins.h" @@ -68,7 +72,6 @@ enum IntrName : uint8_t { INTR_RST55 = 0x2C, // RST 5.5: 002CH INTR_RST65 = 0x34, // RST 6.5: 0034H INTR_RST75 = 0x3C, // RST 7.5: 003CH - INTR_TRAP = 0x24, // TRAP: 0024H }; struct PinsI8085 final : Pins { @@ -85,22 +88,19 @@ struct PinsI8085 final : Pins { uint8_t *buf, uint8_t max); private: - uint8_t _inta; - Signals *cycleT1() const; Signals *cycleT2() const; Signals *cycleT2Pause() const; Signals *cycleT2Ready(uint16_t pc) const; Signals *cycleT3(Signals *signals); void loop(); - bool rawStep(uint16_t pc, bool step); + void suspend(); + bool rawStep(); uint8_t execute(const uint8_t *inst, uint8_t len, uint16_t *addr, uint8_t *buf, uint8_t max); void disassembleCycles(); void printCycles(); - - static uint8_t intrToInta(uint8_t name); }; extern struct PinsI8085 Pins; diff --git a/debugger/i8085/signals_i8085.cpp b/debugger/i8085/signals_i8085.cpp index 319a3ab0..d9fed63d 100644 --- a/debugger/i8085/signals_i8085.cpp +++ b/debugger/i8085/signals_i8085.cpp @@ -8,16 +8,29 @@ namespace debugger { namespace i8085 { void Signals::getAddress() { - s() = busRead(S); - iom() = digitalReadFast(PIN_IOM); addr = busRead(ADDR); + iom() = digitalReadFast(PIN_IOM); + cntl() = busRead(CNTL); } void Signals::getDirection() { - // s() = busRead(S); - rd() = digitalReadFast(PIN_RD); - wr() = digitalReadFast(PIN_WR); - inta() = digitalReadFast(PIN_INTA); + cntl() = busRead(CNTL); +} + +bool Signals::read() const { + return (cntl() & CNTL_RD) == 0; +} + +bool Signals::write() const { + return (cntl() & CNTL_WR) == 0; +} + +bool Signals::fetch() const { + return memory() && (cntl() & CNTL_S) == S_FETCH; +} + +bool Signals::vector() const { + return (cntl() & CNTL_INTA) == 0; } void Signals::getData() { diff --git a/debugger/i8085/signals_i8085.h b/debugger/i8085/signals_i8085.h index 076f711b..4fba17c8 100644 --- a/debugger/i8085/signals_i8085.h +++ b/debugger/i8085/signals_i8085.h @@ -13,11 +13,11 @@ struct Signals final : SignalsBase { void print() const; void setAddress(uint16_t _addr) { addr = _addr; } - bool read() const { return rd() == 0; } - bool write() const { return wr() == 0; } + bool read() const; + bool write() const; bool memory() const { return iom() == 0; } - bool fetch() const { return iom() == 0 && s() == S_FETCH; } - bool vector() const { return inta() == 0; } + bool fetch() const; + bool vector() const; private: enum Status : uint8_t { @@ -27,17 +27,11 @@ struct Signals final : SignalsBase { S_FETCH = 3, // OF or INA }; - Status s() const { return static_cast(_signals[0]); } + uint8_t cntl() const { return _signals[0]; } uint8_t iom() const { return _signals[1]; } - uint8_t rd() const { return _signals[2]; } - uint8_t wr() const { return _signals[3]; } - uint8_t inta() const { return _signals[4]; } - uint8_t &s() { return _signals[0]; } + uint8_t &cntl() { return _signals[0]; } uint8_t &iom() { return _signals[1]; } - uint8_t &rd() { return _signals[2]; } - uint8_t &wr() { return _signals[3]; } - uint8_t &inta() { return _signals[4]; } }; } // namespace i8085 diff --git a/samples/i8085/echo.asm b/samples/i8085/echo.asm index 274046de..8d0c0e08 100644 --- a/samples/i8085/echo.asm +++ b/samples/i8085/echo.asm @@ -17,6 +17,10 @@ RX_EN_TX_EN: equ CMD_RTS_bm|CMD_DTR_bm|CMD_ER_bm|CMD_RxEN_bm|CMD_TxEN_bm stack: equ $ org ORG_RESET + jmp init + + org 0100H +init: lxi sp, stack init_usart: diff --git a/samples/i8085/echo.hex b/samples/i8085/echo.hex index 9d6a43d7..b5927dde 100644 --- a/samples/i8085/echo.hex +++ b/samples/i8085/echo.hex @@ -1,3 +1,4 @@ -:20000000310010AFD301D301D3013E40D30100003E4ED30100003E37D301DB01E602CA1AD1 -:1D00200000DB0047B7CA3C00DB01E601CA280078D300FE0DC21A00060AC32800768C +:03000000C3000139 +:20010000310010AFD301D301D3013E40D30100003E4ED30100003E37D301DB01E602CA1AD0 +:1D01200001DB0047B7CA3C01DB01E601CA280178D300FE0DC21A01060AC328017686 :00000001FF diff --git a/samples/i8085/echo.lst b/samples/i8085/echo.lst index 93aa0619..20371528 100644 --- a/samples/i8085/echo.lst +++ b/samples/i8085/echo.lst @@ -100,43 +100,47 @@ 1000 : =1000 stack: equ $ 1000 : 0 : org ORG_RESET - 0 : 31 00 10 lxi sp, stack + 0 : C3 00 01 jmp init 3 : - 3 : init_usart: - 3 : AF xra a ; clear A - 4 : D3 01 out USARTC - 6 : D3 01 out USARTC - 8 : D3 01 out USARTC ; safest way to sync mode - A : 3E 40 mvi a, CMD_IR_bm - C : D3 01 out USARTC ; reset - E : 00 nop - F : 00 nop - 10 : 3E 4E mvi a, ASYNC_MODE - 12 : D3 01 out USARTC - 14 : 00 nop - 15 : 00 nop - 16 : 3E 37 mvi a, RX_EN_TX_EN - 18 : D3 01 out USARTC - 1A : - 1A : receive_loop: - 1A : DB 01 in USARTS - 1C : E6 02 ani ST_RxRDY_bm - 1E : CA 1A 00 jz receive_loop - 21 : receive_data: - 21 : DB 00 in USARTD - 23 : 47 mov b, a - 24 : B7 ora a - 25 : CA 3C 00 jz halt_to_system - 28 : transmit_loop: - 28 : DB 01 in USARTS - 2A : E6 01 ani ST_TxRDY_bm - 2C : CA 28 00 jz transmit_loop - 2F : transmit_data: - 2F : 78 mov a, b - 30 : D3 00 out USARTD - 32 : FE 0D cpi 0DH - 34 : C2 1A 00 jnz receive_loop - 37 : 06 0A mvi b, 0AH - 39 : C3 28 00 jmp transmit_loop - 3C : halt_to_system: - 3C : 76 hlt + 100 : org 0100H + 100 : init: + 100 : 31 00 10 lxi sp, stack + 103 : + 103 : init_usart: + 103 : AF xra a ; clear A + 104 : D3 01 out USARTC + 106 : D3 01 out USARTC + 108 : D3 01 out USARTC ; safest way to sync mode + 10A : 3E 40 mvi a, CMD_IR_bm + 10C : D3 01 out USARTC ; reset + 10E : 00 nop + 10F : 00 nop + 110 : 3E 4E mvi a, ASYNC_MODE + 112 : D3 01 out USARTC + 114 : 00 nop + 115 : 00 nop + 116 : 3E 37 mvi a, RX_EN_TX_EN + 118 : D3 01 out USARTC + 11A : + 11A : receive_loop: + 11A : DB 01 in USARTS + 11C : E6 02 ani ST_RxRDY_bm + 11E : CA 1A 01 jz receive_loop + 121 : receive_data: + 121 : DB 00 in USARTD + 123 : 47 mov b, a + 124 : B7 ora a + 125 : CA 3C 01 jz halt_to_system + 128 : transmit_loop: + 128 : DB 01 in USARTS + 12A : E6 01 ani ST_TxRDY_bm + 12C : CA 28 01 jz transmit_loop + 12F : transmit_data: + 12F : 78 mov a, b + 130 : D3 00 out USARTD + 132 : FE 0D cpi 0DH + 134 : C2 1A 01 jnz receive_loop + 137 : 06 0A mvi b, 0AH + 139 : C3 28 01 jmp transmit_loop + 13C : halt_to_system: + 13C : 76 hlt diff --git a/samples/i8085/echoir.asm b/samples/i8085/echoir.asm index 03d7a33e..f82e5612 100644 --- a/samples/i8085/echoir.asm +++ b/samples/i8085/echoir.asm @@ -28,6 +28,7 @@ stack: equ $ org ORG_RST7 jmp isr_intr + org 0100H init: lxi sp, stack lxi h, rx_queue diff --git a/samples/i8085/echoir.hex b/samples/i8085/echoir.hex index 528bfbdf..a0e2f8a9 100644 --- a/samples/i8085/echoir.hex +++ b/samples/i8085/echoir.hex @@ -1,9 +1,10 @@ -:03000000C33B00FF -:20003800C3ED003100102100200680CD8B00AFD301D301D3013E40D30100003E4ED30100BB -:20005800003E37D3013E38D3023E00D303FB210020F3CDC900FBD2690047B7CA8A00DB01B7 -:20007800E601CA760078D300FE0DC26900060AC3760076F5E5AF7778DE042377C60247AF4F -:20009800237705C29800E1F1C9D5577E23BE2B7ADAAD00D1C9E53423235E1600EB19232346 -:2000B80077EB7E3C2BBE23DAC300AF771AE1D137C97EB7C2CF00C9D5E5352323237E5F1697 -:2000D80000EB1923EB3C2B2BBE2323DAE700AF771AE1D137C9F5E5DB01E602CAFE00DB006C -:0A00F800210020CDA100E1F1FBC9B9 +:03000000C3000139 +:03003800C3B2014F +:200100003100102100200680CD5001AFD301D301D3013E40D30100003E4ED30100003E3767 +:20012000D3013E38D3023E00D303FB210020F3CD8E01FBD22E0147B7CA4F01DB01E601CA60 +:200140003B0178D300FE0DC22E01060AC33B0176F5E5AF7778DE042377C60247AF23770546 +:20016000C25D01E1F1C9D5577E23BE2B7ADA7201D1C9E53423235E1600EB19232377EB7EB0 +:200180003C2BBE23DA8801AF771AE1D137C97EB7C29401C9D5E5352323237E5F1600EB191E +:2001A00023EB3C2B2BBE2323DAAC01AF771AE1D137C9F5E5DB01E602CAC301DB00210020DA +:0701C000CD6601E1F1FBC96E :00000001FF diff --git a/samples/i8085/echoir.lst b/samples/i8085/echoir.lst index e9e6f002..5bfa514c 100644 --- a/samples/i8085/echoir.lst +++ b/samples/i8085/echoir.lst @@ -106,189 +106,190 @@ 1000 : =1000 stack: equ $ 1000 : 0 : org ORG_RESET - 0 : C3 3B 00 jmp init + 0 : C3 00 01 jmp init 3 : 38 : org ORG_RST7 - 38 : C3 ED 00 jmp isr_intr + 38 : C3 B2 01 jmp isr_intr 3B : - 3B : init: - 3B : 31 00 10 lxi sp, stack - 3E : 21 00 20 lxi h, rx_queue - 41 : 06 80 mvi b, rx_queue_size - 43 : CD 8B 00 call queue_init - 46 : init_usart: - 46 : AF xra a ; clear A - 47 : D3 01 out USARTC - 49 : D3 01 out USARTC - 4B : D3 01 out USARTC ; safest way to sync mode - 4D : 3E 40 mvi a, CMD_IR_bm - 4F : D3 01 out USARTC ; reset - 51 : 00 nop - 52 : 00 nop - 53 : 3E 4E mvi a, ASYNC_MODE - 55 : D3 01 out USARTC - 57 : 00 nop - 58 : 00 nop - 59 : 3E 37 mvi a, RX_EN_TX_EN - 5B : D3 01 out USARTC - 5D : 3E 38 mvi a, ORG_RST7 - 5F : D3 02 out USARTRV ; enable RxRDY interrupt using RST 7 - 61 : 3E 00 mvi a, ORG_RESET - 63 : D3 03 out USARTTV ; disable TxRDY interrupt - 65 : - 65 : FB ei - 66 : - 66 : 21 00 20 lxi h, rx_queue - 69 : receive_loop: - 69 : F3 di ; Disable INTR - 6A : CD C9 00 call queue_remove - 6D : FB ei ; Enable INTR - 6E : D2 69 00 jnc receive_loop - 71 : 47 mov b, a ; save character - 72 : B7 ora a - 73 : CA 8A 00 jz halt_to_system - 76 : transmit_loop: - 76 : DB 01 in USARTC - 78 : E6 01 ani ST_TxRDY_bm - 7A : CA 76 00 jz transmit_loop - 7D : transmit_data: - 7D : 78 mov a, b - 7E : D3 00 out USARTD - 80 : FE 0D cpi 0DH - 82 : C2 69 00 jnz receive_loop - 85 : 06 0A mvi b, 0AH - 87 : C3 76 00 jmp transmit_loop - 8A : halt_to_system: - 8A : 76 hlt - 8B : - 8B : include "queue.inc" -(1) 8B : ;;; -*- mode: asm; mode: flyspell-prog; -*- -(1) 8B : ;;; [queue] queue structure -(1) 8B : =0 queue_len: equ 0 ; queue length -(1) 8B : =1 queue_size: equ 1 ; buffer size -(1) 8B : =2 queue_put: equ 2 ; queue put index -(1) 8B : =3 queue_get: equ 3 ; queue get index -(1) 8B : =4 queue_buf: equ 4 ; buffer start offset -(1) 8B : -(1) 8B : ;;; [queue] Initialize queue -(1) 8B : ;;; @param HL queue work space pointer -(1) 8B : ;;; @param B queue work space size -(1) 8B : ;;; @clobber B -(1) 8B : queue_init: -(1) 8B : F5 push psw -(1) 8C : E5 push h -(1) 8D : AF xra a -(1) 8E : 77 mov m, a ; queue_len -(1) 8F : 78 mov a, b -(1) 90 : DE 04 sbi queue_buf -(1) 92 : 23 inx h -(1) 93 : 77 mov m, a ; queue_size -(1) 94 : C6 02 adi 2 ; for queue_put and queue_get -(1) 96 : 47 mov b,a -(1) 97 : AF xra a -(1) 98 : queue_init_loop: -(1) 98 : 23 inx h -(1) 99 : 77 mov m, a -(1) 9A : 05 dcr b -(1) 9B : C2 98 00 jnz queue_init_loop -(1) 9E : E1 pop h -(1) 9F : F1 pop psw -(1) A0 : C9 ret -(1) A1 : -(1) A1 : ;;; [queue] Add an element to queue -(1) A1 : ;;; @param HL queue work space pointer -(1) A1 : ;;; @param A an element -(1) A1 : ;;; @return F.C 0 if queue is full -(1) A1 : queue_add: -(1) A1 : D5 push d -(1) A2 : 57 mov d, a ; save an element -(1) A3 : 7E mov a, m ; queue_len -(1) A4 : 23 inx h -(1) A5 : BE cmp m ; queue_size -(1) A6 : 2B dcx h -(1) A7 : 7A mov a, d ; restore an element -(1) A8 : DA AD 00 jc queue_add_store ; queue_len < queue_size -(1) AB : D1 pop d ; cleared carry is ensured by |jc| -(1) AC : C9 ret -(1) AD : queue_add_store: -(1) AD : E5 push h -(1) AE : 34 inr m ; queue_len++ -(1) AF : 23 inx h -(1) B0 : 23 inx h -(1) B1 : 5E mov e, m ; queue_put -(1) B2 : 16 00 mvi d, 0 -(1) B4 : EB xchg ; DE points queue_put -(1) B5 : 19 dad d -(1) B6 : 23 inx h -(1) B7 : 23 inx h ; offset of queue_buf -(1) B8 : 77 mov m, a ; store an element -(1) B9 : EB xchg ; DE points a stored element -(1) BA : 7E mov a, m ; queue_put -(1) BB : 3C inr a ; queue_put++ -(1) BC : 2B dcx h -(1) BD : BE cmp m ; queue_size -(1) BE : 23 inx h -(1) BF : DA C3 00 jc queue_add_update ; queue_put < queue_size -(1) C2 : AF xra a ; wrap around -(1) C3 : queue_add_update: -(1) C3 : 77 mov m, a ; queue_put -(1) C4 : 1A ldax d ; restore an element -(1) C5 : E1 pop h -(1) C6 : D1 pop d -(1) C7 : 37 stc ; set carry -(1) C8 : C9 ret -(1) C9 : -(1) C9 : ;;; [queue] Remove an element from queue -(1) C9 : ;;; @param HL queue work space pointer -(1) C9 : ;;; @return A an element -(1) C9 : ;;; @return F.C 0 if queue is empty -(1) C9 : queue_remove: -(1) C9 : 7E mov a, m ; queue_len -(1) CA : B7 ora a ; clear carry -(1) CB : C2 CF 00 jnz queue_remove_elem ; queue_len > 0 -(1) CE : C9 ret ; carry is cleared by |ora| -(1) CF : queue_remove_elem: -(1) CF : D5 push d -(1) D0 : E5 push h -(1) D1 : 35 dcr m ; queue_len-- -(1) D2 : 23 inx h -(1) D3 : 23 inx h -(1) D4 : 23 inx h -(1) D5 : 7E mov a, m ; queue_get -(1) D6 : 5F mov e, a -(1) D7 : 16 00 mvi d, 0 -(1) D9 : EB xchg ; DE points queue_get -(1) DA : 19 dad d -(1) DB : 23 inx h ; offset of queue_buf -(1) DC : EB xchg ; DE points an element to read -(1) DD : 3C inr a ; queue_get++ -(1) DE : 2B dcx h -(1) DF : 2B dcx h -(1) E0 : BE cmp m ; queue_size -(1) E1 : 23 inx h -(1) E2 : 23 inx h -(1) E3 : DA E7 00 jc queue_remove_update ; queue_get < queue_size -(1) E6 : AF xra a ; wrap around -(1) E7 : queue_remove_update: -(1) E7 : 77 mov m, a ; queue_get -(1) E8 : 1A ldax d ; read an element -(1) E9 : E1 pop h -(1) EA : D1 pop d -(1) EB : 37 stc ; set carry -(1) EC : C9 ret - ED : - ED : isr_intr: - ED : F5 push psw - EE : E5 push h - EF : DB 01 in USARTS - F1 : isr_intr_receive: - F1 : E6 02 ani ST_RxRDY_bm - F3 : CA FE 00 jz isr_intr_recv_end - F6 : DB 00 in USARTD - F8 : 21 00 20 lxi h, rx_queue - FB : CD A1 00 call queue_add - FE : isr_intr_recv_end: - FE : E1 pop h - FF : F1 pop psw - 100 : FB ei - 101 : C9 ret + 100 : org 0100H + 100 : init: + 100 : 31 00 10 lxi sp, stack + 103 : 21 00 20 lxi h, rx_queue + 106 : 06 80 mvi b, rx_queue_size + 108 : CD 50 01 call queue_init + 10B : init_usart: + 10B : AF xra a ; clear A + 10C : D3 01 out USARTC + 10E : D3 01 out USARTC + 110 : D3 01 out USARTC ; safest way to sync mode + 112 : 3E 40 mvi a, CMD_IR_bm + 114 : D3 01 out USARTC ; reset + 116 : 00 nop + 117 : 00 nop + 118 : 3E 4E mvi a, ASYNC_MODE + 11A : D3 01 out USARTC + 11C : 00 nop + 11D : 00 nop + 11E : 3E 37 mvi a, RX_EN_TX_EN + 120 : D3 01 out USARTC + 122 : 3E 38 mvi a, ORG_RST7 + 124 : D3 02 out USARTRV ; enable RxRDY interrupt using RST 7 + 126 : 3E 00 mvi a, ORG_RESET + 128 : D3 03 out USARTTV ; disable TxRDY interrupt + 12A : + 12A : FB ei + 12B : + 12B : 21 00 20 lxi h, rx_queue + 12E : receive_loop: + 12E : F3 di ; Disable INTR + 12F : CD 8E 01 call queue_remove + 132 : FB ei ; Enable INTR + 133 : D2 2E 01 jnc receive_loop + 136 : 47 mov b, a ; save character + 137 : B7 ora a + 138 : CA 4F 01 jz halt_to_system + 13B : transmit_loop: + 13B : DB 01 in USARTC + 13D : E6 01 ani ST_TxRDY_bm + 13F : CA 3B 01 jz transmit_loop + 142 : transmit_data: + 142 : 78 mov a, b + 143 : D3 00 out USARTD + 145 : FE 0D cpi 0DH + 147 : C2 2E 01 jnz receive_loop + 14A : 06 0A mvi b, 0AH + 14C : C3 3B 01 jmp transmit_loop + 14F : halt_to_system: + 14F : 76 hlt + 150 : + 150 : include "queue.inc" +(1) 150 : ;;; -*- mode: asm; mode: flyspell-prog; -*- +(1) 150 : ;;; [queue] queue structure +(1) 150 : =0 queue_len: equ 0 ; queue length +(1) 150 : =1 queue_size: equ 1 ; buffer size +(1) 150 : =2 queue_put: equ 2 ; queue put index +(1) 150 : =3 queue_get: equ 3 ; queue get index +(1) 150 : =4 queue_buf: equ 4 ; buffer start offset +(1) 150 : +(1) 150 : ;;; [queue] Initialize queue +(1) 150 : ;;; @param HL queue work space pointer +(1) 150 : ;;; @param B queue work space size +(1) 150 : ;;; @clobber B +(1) 150 : queue_init: +(1) 150 : F5 push psw +(1) 151 : E5 push h +(1) 152 : AF xra a +(1) 153 : 77 mov m, a ; queue_len +(1) 154 : 78 mov a, b +(1) 155 : DE 04 sbi queue_buf +(1) 157 : 23 inx h +(1) 158 : 77 mov m, a ; queue_size +(1) 159 : C6 02 adi 2 ; for queue_put and queue_get +(1) 15B : 47 mov b,a +(1) 15C : AF xra a +(1) 15D : queue_init_loop: +(1) 15D : 23 inx h +(1) 15E : 77 mov m, a +(1) 15F : 05 dcr b +(1) 160 : C2 5D 01 jnz queue_init_loop +(1) 163 : E1 pop h +(1) 164 : F1 pop psw +(1) 165 : C9 ret +(1) 166 : +(1) 166 : ;;; [queue] Add an element to queue +(1) 166 : ;;; @param HL queue work space pointer +(1) 166 : ;;; @param A an element +(1) 166 : ;;; @return F.C 0 if queue is full +(1) 166 : queue_add: +(1) 166 : D5 push d +(1) 167 : 57 mov d, a ; save an element +(1) 168 : 7E mov a, m ; queue_len +(1) 169 : 23 inx h +(1) 16A : BE cmp m ; queue_size +(1) 16B : 2B dcx h +(1) 16C : 7A mov a, d ; restore an element +(1) 16D : DA 72 01 jc queue_add_store ; queue_len < queue_size +(1) 170 : D1 pop d ; cleared carry is ensured by |jc| +(1) 171 : C9 ret +(1) 172 : queue_add_store: +(1) 172 : E5 push h +(1) 173 : 34 inr m ; queue_len++ +(1) 174 : 23 inx h +(1) 175 : 23 inx h +(1) 176 : 5E mov e, m ; queue_put +(1) 177 : 16 00 mvi d, 0 +(1) 179 : EB xchg ; DE points queue_put +(1) 17A : 19 dad d +(1) 17B : 23 inx h +(1) 17C : 23 inx h ; offset of queue_buf +(1) 17D : 77 mov m, a ; store an element +(1) 17E : EB xchg ; DE points a stored element +(1) 17F : 7E mov a, m ; queue_put +(1) 180 : 3C inr a ; queue_put++ +(1) 181 : 2B dcx h +(1) 182 : BE cmp m ; queue_size +(1) 183 : 23 inx h +(1) 184 : DA 88 01 jc queue_add_update ; queue_put < queue_size +(1) 187 : AF xra a ; wrap around +(1) 188 : queue_add_update: +(1) 188 : 77 mov m, a ; queue_put +(1) 189 : 1A ldax d ; restore an element +(1) 18A : E1 pop h +(1) 18B : D1 pop d +(1) 18C : 37 stc ; set carry +(1) 18D : C9 ret +(1) 18E : +(1) 18E : ;;; [queue] Remove an element from queue +(1) 18E : ;;; @param HL queue work space pointer +(1) 18E : ;;; @return A an element +(1) 18E : ;;; @return F.C 0 if queue is empty +(1) 18E : queue_remove: +(1) 18E : 7E mov a, m ; queue_len +(1) 18F : B7 ora a ; clear carry +(1) 190 : C2 94 01 jnz queue_remove_elem ; queue_len > 0 +(1) 193 : C9 ret ; carry is cleared by |ora| +(1) 194 : queue_remove_elem: +(1) 194 : D5 push d +(1) 195 : E5 push h +(1) 196 : 35 dcr m ; queue_len-- +(1) 197 : 23 inx h +(1) 198 : 23 inx h +(1) 199 : 23 inx h +(1) 19A : 7E mov a, m ; queue_get +(1) 19B : 5F mov e, a +(1) 19C : 16 00 mvi d, 0 +(1) 19E : EB xchg ; DE points queue_get +(1) 19F : 19 dad d +(1) 1A0 : 23 inx h ; offset of queue_buf +(1) 1A1 : EB xchg ; DE points an element to read +(1) 1A2 : 3C inr a ; queue_get++ +(1) 1A3 : 2B dcx h +(1) 1A4 : 2B dcx h +(1) 1A5 : BE cmp m ; queue_size +(1) 1A6 : 23 inx h +(1) 1A7 : 23 inx h +(1) 1A8 : DA AC 01 jc queue_remove_update ; queue_get < queue_size +(1) 1AB : AF xra a ; wrap around +(1) 1AC : queue_remove_update: +(1) 1AC : 77 mov m, a ; queue_get +(1) 1AD : 1A ldax d ; read an element +(1) 1AE : E1 pop h +(1) 1AF : D1 pop d +(1) 1B0 : 37 stc ; set carry +(1) 1B1 : C9 ret + 1B2 : + 1B2 : isr_intr: + 1B2 : F5 push psw + 1B3 : E5 push h + 1B4 : DB 01 in USARTS + 1B6 : isr_intr_receive: + 1B6 : E6 02 ani ST_RxRDY_bm + 1B8 : CA C3 01 jz isr_intr_recv_end + 1BB : DB 00 in USARTD + 1BD : 21 00 20 lxi h, rx_queue + 1C0 : CD 66 01 call queue_add + 1C3 : isr_intr_recv_end: + 1C3 : E1 pop h + 1C4 : F1 pop psw + 1C5 : FB ei + 1C6 : C9 ret diff --git a/samples/i8085/sio.asm b/samples/i8085/sio.asm index 6599c317..5ed4f373 100644 --- a/samples/i8085/sio.asm +++ b/samples/i8085/sio.asm @@ -6,6 +6,10 @@ stack: equ $ org ORG_RESET + jmp init + + org 0100H +init: lxi sp, stack mvi a, SIM_SOD OR SIM_SDE sim ; set mark diff --git a/samples/i8085/sio.hex b/samples/i8085/sio.hex index c450564d..4a9f0efb 100644 --- a/samples/i8085/sio.hex +++ b/samples/i8085/sio.hex @@ -1,6 +1,7 @@ -:200000003100103EC030CD1E00B7CA1D00CD5200FE0DC206003E0ACD5200C3060076C5D5B6 -:2000200020E680CA200020E680C22600161DCD8A000E081E0020E680477B0FB05F1610CDCB -:200040008A000000000DC23500161ACD8A007BD1C1C9F5C5D5473EC0300E083E40301611C6 -:20006000CD8A00780F47E680F640000000301610CD8A000DC26300C37A00C37D00003EC065 -:0F008000301613CD8A00D1C1F1C915C28A00C94B +:03000000C3000139 +:200100003100103EC030CD1E01B7CA1D01CD5201FE0DC206013E0ACD5201C3060176C5D5AF +:2001200020E680CA200120E680C22601161DCD8A010E081E0020E680477B0FB05F1610CDC7 +:200140008A010000000DC23501161ACD8A017BD1C1C9F5C5D5473EC0300E083E40301611C2 +:20016000CD8A01780F47E680F640000000301610CD8A010DC26301C37A01C37D01003EC05F +:0F018000301613CD8A01D1C1F1C915C28A01C948 :00000001FF diff --git a/samples/i8085/sio.lst b/samples/i8085/sio.lst index f840eb78..644ff249 100644 --- a/samples/i8085/sio.lst +++ b/samples/i8085/sio.lst @@ -49,108 +49,112 @@ 1000 : =1000 stack: equ $ 1000 : 0 : org ORG_RESET - 0 : 31 00 10 lxi sp, stack - 3 : 3E C0 mvi a, SIM_SOD OR SIM_SDE - 5 : 30 sim ; set mark - 6 : - 6 : echo: - 6 : CD 1E 00 call getch - 9 : B7 ora a - A : CA 1D 00 jz halt_to_system - D : echo_back: - D : CD 52 00 call putch - 10 : FE 0D cpi 0DH - 12 : C2 06 00 jnz echo - 15 : 3E 0A mvi a,0AH - 17 : CD 52 00 call putch - 1A : C3 06 00 jmp echo - 1D : halt_to_system: - 1D : 76 hlt - 1E : - 1E : ;;; Assume that 8085 is running with 3MHz CLK. - 1E : ;;; 9,600bps bit duration = 3,000,000/9,600 = 312.5 CLK - 1E : - 1E : ;;; SID is latched at T3/CLK=0 of RIM instruction - 1E : C5 getch: push b ;12 - 1F : D5 push d ;12 - 20 : 20 get1: rim ;4 - 21 : E6 80 ani RIM_SID ;7 - 23 : CA 20 00 jz get1 ;7/10 - 26 : 20 get2: rim ;4,4 - 27 : E6 80 ani RIM_SID ;7,11 - 29 : C2 26 00 jnz get2 ;7/10,18 wait start bit - 2C : ;;; 470 = 312.5*1.504 - 2C : 16 1D mvi d,29 ;7,25 - 2E : CD 8A 00 call delay ;29*14+25,456 - 31 : 0E 08 mvi c,8 ;7,463 - 33 : 1E 00 mvi e,0 ;7,470 - 35 : ;;; - 35 : 20 get3: rim ;4,4 - 36 : E6 80 ani RIM_SID ;7,11 - 38 : 47 mov b,a ;4,15 - 39 : 7B mov a,e ;4,19 - 3A : 0F rrc ;4,23 - 3B : B0 ora b ;4,27 - 3C : 5F mov e,a ;4,31 - 3D : 16 10 mvi d,16 ;7,38 - 3F : CD 8A 00 call delay ;16*14+25,287 - 42 : 00 nop ;4,291 - 43 : 00 nop ;4,295 - 44 : 00 nop ;4,299 - 45 : 0D dcr c ;4,303 - 46 : C2 35 00 jnz get3 ;7/10,313,310 - 49 : ;;; 706 = 312.5*2.259 - 49 : 16 1A mvi d,26 ;7,317 - 4B : CD 8A 00 call delay ;26*14+25,706 - 4E : 7B mov a,e ;4 - 4F : D1 pop d ;10 - 50 : C1 pop b ;10 - 51 : C9 ret ;10 - 52 : - 52 : ;;; SOD is set at T2/CLK=0 of SIM instruciton - 52 : F5 putch: push psw ;12 - 53 : C5 push b ;12 - 54 : D5 push d ;12 - 55 : 47 mov b,a ;4 - 56 : 3E C0 mvi a,SIM_SOD OR SIM_SDE ;7 - 58 : 30 sim ;4 set mark - 59 : 0E 08 mvi c,8 ;7 - 5B : ;;; 4+7+17*14+25+4*6+7*2 = 312 - 5B : 3E 40 mvi a,SIM_SDE ;7 start bit - 5D : 30 sim ;4,4 - 5E : 16 11 mvi d,17 ;7,11 - 60 : CD 8A 00 call delay ;17*14+25,274 - 63 : ;;; 4*8+7*3+10+16*14+25 = 312 - 63 : 78 put1: mov a,b ;4,278 - 64 : 0F rrc ;4.282 - 65 : 47 mov b,a ;4,286 - 66 : E6 80 ani 80H ;7,293 data bit - 68 : F6 40 ori SIM_SDE ;7,300 - 6A : 00 nop ;4,304 - 6B : 00 nop ;4,308 - 6C : 00 nop ;4,312 - 6D : 30 sim ;4,4 - 6E : 16 10 mvi d,16 ;7,11 - 70 : CD 8A 00 call delay ;16*14+25,260 - 73 : 0D dcr c ;4,264 - 74 : C2 63 00 jnz put1 ;7/10,274,271 - 77 : ;;; 4*2+7*2+16*14+25+10*2+4+7 - 77 : C3 7A 00 jmp $+3 ;10,281 - 7A : C3 7D 00 jmp $+3 ;10,291 - 7D : 00 nop ;4,295 - 7E : 3E C0 mvi a,SIM_SOD OR SIM_SDE ;7,302 stop bit - 80 : ;;; - 80 : 30 sim ;4,306 - 81 : 16 13 mvi d,19 ;7,313 - 83 : CD 8A 00 call delay ;19*14+25,604 - 86 : ;;; - 86 : D1 pop d ;10 - 87 : C1 pop b ;10 - 88 : F1 pop psw ;10 - 89 : C9 ret ;10 - 8A : - 8A : ;;; delay D*14+25 (18+D*14-3+10) - 8A : ;;; call delay ;18 - 8A : 15 delay: dcr d ;4 - 8B : C2 8A 00 jnz delay ;7/10 - 8E : C9 ret ;10 + 0 : C3 00 01 jmp init + 3 : + 100 : org 0100H + 100 : init: + 100 : 31 00 10 lxi sp, stack + 103 : 3E C0 mvi a, SIM_SOD OR SIM_SDE + 105 : 30 sim ; set mark + 106 : + 106 : echo: + 106 : CD 1E 01 call getch + 109 : B7 ora a + 10A : CA 1D 01 jz halt_to_system + 10D : echo_back: + 10D : CD 52 01 call putch + 110 : FE 0D cpi 0DH + 112 : C2 06 01 jnz echo + 115 : 3E 0A mvi a,0AH + 117 : CD 52 01 call putch + 11A : C3 06 01 jmp echo + 11D : halt_to_system: + 11D : 76 hlt + 11E : + 11E : ;;; Assume that 8085 is running with 3MHz CLK. + 11E : ;;; 9,600bps bit duration = 3,000,000/9,600 = 312.5 CLK + 11E : + 11E : ;;; SID is latched at T3/CLK=0 of RIM instruction + 11E : C5 getch: push b ;12 + 11F : D5 push d ;12 + 120 : 20 get1: rim ;4 + 121 : E6 80 ani RIM_SID ;7 + 123 : CA 20 01 jz get1 ;7/10 + 126 : 20 get2: rim ;4,4 + 127 : E6 80 ani RIM_SID ;7,11 + 129 : C2 26 01 jnz get2 ;7/10,18 wait start bit + 12C : ;;; 470 = 312.5*1.504 + 12C : 16 1D mvi d,29 ;7,25 + 12E : CD 8A 01 call delay ;29*14+25,456 + 131 : 0E 08 mvi c,8 ;7,463 + 133 : 1E 00 mvi e,0 ;7,470 + 135 : ;;; + 135 : 20 get3: rim ;4,4 + 136 : E6 80 ani RIM_SID ;7,11 + 138 : 47 mov b,a ;4,15 + 139 : 7B mov a,e ;4,19 + 13A : 0F rrc ;4,23 + 13B : B0 ora b ;4,27 + 13C : 5F mov e,a ;4,31 + 13D : 16 10 mvi d,16 ;7,38 + 13F : CD 8A 01 call delay ;16*14+25,287 + 142 : 00 nop ;4,291 + 143 : 00 nop ;4,295 + 144 : 00 nop ;4,299 + 145 : 0D dcr c ;4,303 + 146 : C2 35 01 jnz get3 ;7/10,313,310 + 149 : ;;; 706 = 312.5*2.259 + 149 : 16 1A mvi d,26 ;7,317 + 14B : CD 8A 01 call delay ;26*14+25,706 + 14E : 7B mov a,e ;4 + 14F : D1 pop d ;10 + 150 : C1 pop b ;10 + 151 : C9 ret ;10 + 152 : + 152 : ;;; SOD is set at T2/CLK=0 of SIM instruciton + 152 : F5 putch: push psw ;12 + 153 : C5 push b ;12 + 154 : D5 push d ;12 + 155 : 47 mov b,a ;4 + 156 : 3E C0 mvi a,SIM_SOD OR SIM_SDE ;7 + 158 : 30 sim ;4 set mark + 159 : 0E 08 mvi c,8 ;7 + 15B : ;;; 4+7+17*14+25+4*6+7*2 = 312 + 15B : 3E 40 mvi a,SIM_SDE ;7 start bit + 15D : 30 sim ;4,4 + 15E : 16 11 mvi d,17 ;7,11 + 160 : CD 8A 01 call delay ;17*14+25,274 + 163 : ;;; 4*8+7*3+10+16*14+25 = 312 + 163 : 78 put1: mov a,b ;4,278 + 164 : 0F rrc ;4.282 + 165 : 47 mov b,a ;4,286 + 166 : E6 80 ani 80H ;7,293 data bit + 168 : F6 40 ori SIM_SDE ;7,300 + 16A : 00 nop ;4,304 + 16B : 00 nop ;4,308 + 16C : 00 nop ;4,312 + 16D : 30 sim ;4,4 + 16E : 16 10 mvi d,16 ;7,11 + 170 : CD 8A 01 call delay ;16*14+25,260 + 173 : 0D dcr c ;4,264 + 174 : C2 63 01 jnz put1 ;7/10,274,271 + 177 : ;;; 4*2+7*2+16*14+25+10*2+4+7 + 177 : C3 7A 01 jmp $+3 ;10,281 + 17A : C3 7D 01 jmp $+3 ;10,291 + 17D : 00 nop ;4,295 + 17E : 3E C0 mvi a,SIM_SOD OR SIM_SDE ;7,302 stop bit + 180 : ;;; + 180 : 30 sim ;4,306 + 181 : 16 13 mvi d,19 ;7,313 + 183 : CD 8A 01 call delay ;19*14+25,604 + 186 : ;;; + 186 : D1 pop d ;10 + 187 : C1 pop b ;10 + 188 : F1 pop psw ;10 + 189 : C9 ret ;10 + 18A : + 18A : ;;; delay D*14+25 (18+D*14-3+10) + 18A : ;;; call delay ;18 + 18A : 15 delay: dcr d ;4 + 18B : C2 8A 01 jnz delay ;7/10 + 18E : C9 ret ;10 diff --git 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4c781d17-b173-4679-bcb5-3b5ae99c9edf)) + (pad "40" thru_hole oval (at 15.24 0) (size 1.6 1.6) (drill 0.8) (layers "*.Cu" "*.Mask") (tstamp 94b36ccd-4b70-4ec2-b9e7-d2f4d9d18264)) + (model "${KICAD6_3DMODEL_DIR}/Package_DIP.3dshapes/DIP-40_W15.24mm_Socket.wrl" + (offset (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) +) diff --git a/schematics/p8085/0-LocalLibrary/DIP-48_W7.62mm.kicad_mod b/schematics/p8085/0-LocalLibrary/DIP-48_W7.62mm.kicad_mod deleted file mode 100644 index 0814a8e4..00000000 --- a/schematics/p8085/0-LocalLibrary/DIP-48_W7.62mm.kicad_mod +++ /dev/null @@ -1,87 +0,0 @@ -(module DIP-48_W7.62mm (layer F.Cu) (tedit 6198C9C5) - (descr "48-lead dip package, row spacing 7.62 mm (300 mils)") - (tags "DIL DIP PDIP 2.54mm 7.62mm 300mill") - (fp_text reference REF** (at 3.81 -2.39) (layer F.SilkS) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_text value DIP-48_W7.62mm (at 5.08 60.96) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_text user %R (at 3.81 19.05) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_line (start 1.255 -1.27) (end 7.365 -1.27) (layer F.Fab) (width 0.1)) - (fp_line (start 7.365 -1.27) (end 7.365 39.37) (layer F.Fab) (width 0.1)) - (fp_line (start 0.255 39.37) (end 0.255 -0.27) (layer F.Fab) (width 0.1)) - (fp_line (start 0.255 -0.27) (end 1.255 -1.27) (layer F.Fab) (width 0.1)) - (fp_line (start 2.81 -1.39) (end 1.04 -1.39) (layer F.SilkS) (width 0.12)) - (fp_line (start 1.04 -1.39) (end 1.04 39.49) (layer F.SilkS) (width 0.12)) - (fp_line (start 6.58 39.49) (end 6.58 -1.39) (layer F.SilkS) (width 0.12)) - (fp_line (start 6.58 -1.39) (end 4.81 -1.39) (layer F.SilkS) (width 0.12)) - (fp_line (start -1.1 -1.6) (end -1.1 39.7) (layer F.CrtYd) (width 0.05)) - (fp_line (start 8.68 39.7) (end 8.68 -1.6) (layer F.CrtYd) (width 0.05)) - (fp_line (start 8.68 -1.6) (end -1.1 -1.6) (layer F.CrtYd) (width 0.05)) - (fp_arc (start 3.81 -1.39) (end 2.81 -1.39) (angle -180) (layer F.SilkS) (width 0.12)) - (fp_line (start 7.365 19.05) (end 7.365 59.69) (layer F.Fab) (width 0.1)) - (fp_line (start 1.04 18.93) (end 1.04 59.81) (layer F.SilkS) (width 0.12)) - (fp_line (start 1.04 59.81) (end 6.58 59.81) (layer F.SilkS) (width 0.12)) - (fp_line (start 6.58 59.81) (end 6.58 18.93) (layer F.SilkS) (width 0.12)) - (fp_line (start -1.1 18.72) (end -1.1 60.02) (layer F.CrtYd) (width 0.05)) - (fp_line (start -1.1 60.02) (end 8.68 60.02) (layer F.CrtYd) (width 0.05)) - (fp_line (start 0.255 59.69) (end 0.255 20.05) (layer F.Fab) (width 0.1)) - (fp_line (start 7.365 59.69) (end 0.255 59.69) (layer F.Fab) (width 0.1)) - (fp_line (start 8.68 60.02) (end 8.68 18.72) (layer F.CrtYd) (width 0.05)) - (pad 1 thru_hole rect (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) - (pad 33 thru_hole oval (at 7.62 38.1) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) - (pad 2 thru_hole oval (at 0 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) - (pad 34 thru_hole oval (at 7.62 35.56) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) - (pad 3 thru_hole oval (at 0 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) - (pad 35 thru_hole oval (at 7.62 33.02) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) - (pad 4 thru_hole oval (at 0 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) - (pad 36 thru_hole oval (at 7.62 30.48) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) - (pad 5 thru_hole oval (at 0 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) - (pad 37 thru_hole oval (at 7.62 27.94) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) - (pad 6 thru_hole oval (at 0 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) - (pad 38 thru_hole oval (at 7.62 25.4) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) - (pad 7 thru_hole oval (at 0 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) - (pad 39 thru_hole oval (at 7.62 22.86) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) - (pad 8 thru_hole oval (at 0 17.78) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) - (pad 40 thru_hole oval (at 7.62 20.32) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) - (pad 9 thru_hole oval (at 0 20.32) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) - (pad 41 thru_hole oval (at 7.62 17.78) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) - (pad 10 thru_hole oval (at 0 22.86) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) - (pad 42 thru_hole oval (at 7.62 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) - (pad 11 thru_hole oval (at 0 25.4) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) - (pad 43 thru_hole oval (at 7.62 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) - (pad 12 thru_hole oval (at 0 27.94) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) - (pad 44 thru_hole oval (at 7.62 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) - (pad 13 thru_hole oval (at 0 30.48) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) - (pad 45 thru_hole oval (at 7.62 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) - (pad 14 thru_hole oval (at 0 33.02) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) - (pad 46 thru_hole oval (at 7.62 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) - (pad 15 thru_hole oval (at 0 35.56) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) - (pad 47 thru_hole oval (at 7.62 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) - (pad 16 thru_hole oval (at 0 38.1) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) - (pad 48 thru_hole oval (at 7.62 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) - (pad 19 thru_hole oval (at 0 45.72) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) - (pad 26 thru_hole oval (at 7.62 55.88) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) - (pad 32 thru_hole oval (at 7.62 40.64) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) - (pad 29 thru_hole oval (at 7.62 48.26) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) - (pad 28 thru_hole oval (at 7.62 50.8) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) - (pad 31 thru_hole oval (at 7.62 43.18) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) - (pad 18 thru_hole oval (at 0 43.18) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) - (pad 27 thru_hole oval (at 7.62 53.34) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) - (pad 22 thru_hole oval (at 0 53.34) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) - (pad 17 thru_hole oval (at 0 40.64) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) - (pad 21 thru_hole oval (at 0 50.8) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) - (pad 30 thru_hole oval (at 7.62 45.72) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) - (pad 23 thru_hole oval (at 0 55.88) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) - (pad 25 thru_hole oval (at 7.62 58.42) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) - (pad 24 thru_hole oval (at 0 58.42) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) - (pad 20 thru_hole oval (at 0 48.26) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) - (model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-32_W7.62mm.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 0)) - ) -) diff --git a/schematics/p8085/0-LocalLibrary/LED_CSL1901UW1_ROM.kicad_mod b/schematics/p8085/0-LocalLibrary/LED_CSL1901UW1_ROM.kicad_mod new file mode 100644 index 00000000..dd6a92a3 --- /dev/null +++ b/schematics/p8085/0-LocalLibrary/LED_CSL1901UW1_ROM.kicad_mod @@ -0,0 +1,90 @@ +(footprint "LED_CSL1901UW1_ROM" (version 20221018) (generator pcbnew) + (layer "F.Cu") + (tags "CSL1901UW1 ") + (attr smd) + (fp_text reference "REF**" (at 3.556 0 unlocked) (layer "F.SilkS") + (effects (font (size 1 1) (thickness 0.15))) + (tstamp 297bc265-9058-4cab-9ceb-a26d71d6ada3) + ) + (fp_text value "LED_CSL1901UW1_ROM" (at 0 0 unlocked) (layer "F.Fab") + (effects (font (size 1 1) (thickness 0.15))) + (tstamp fc907ef8-5e97-44c2-9f33-686b87b426ed) + ) + (fp_text user "${REFERENCE}" (at 0 0 unlocked) (layer "F.Fab") + (effects (font (size 1 1) (thickness 0.15))) + (tstamp 7ce4f04a-5121-4dd5-ad0f-0c9f48bdd407) + ) + (fp_circle (center -1.778 0.508) (end -1.7018 0.508) + (stroke (width 0.1524) (type solid)) (fill none) (layer "F.SilkS") (tstamp 535faaa3-319f-46a7-96be-f18b1484bc28)) + (fp_line (start -1.4097 -0.6096) (end -1.0541 -0.6096) + (stroke (width 0.1524) (type solid)) (layer "F.CrtYd") (tstamp c6e0ca39-775b-4673-9917-6641a8a1cbf9)) + (fp_line (start -1.4097 0.6096) (end -1.4097 -0.6096) + (stroke (width 0.1524) (type solid)) (layer "F.CrtYd") (tstamp a8276677-c43f-4495-b7cf-fde771f4fbf4)) + (fp_line (start -1.0541 -0.6604) (end 1.0541 -0.6604) + (stroke (width 0.1524) (type solid)) (layer "F.CrtYd") (tstamp bb1f4d52-feaa-4ee9-97c4-906b33c40a99)) + (fp_line (start -1.0541 -0.6096) (end -1.0541 -0.6604) + (stroke (width 0.1524) (type solid)) (layer "F.CrtYd") (tstamp 5de3dd3c-3b8f-486d-9e1f-6445e60040ba)) + (fp_line (start -1.0541 0.6096) (end -1.4097 0.6096) + (stroke (width 0.1524) (type solid)) (layer "F.CrtYd") (tstamp 7f539cdb-3878-4848-86b1-2a3e87412729)) + (fp_line (start -1.0541 0.6604) (end -1.0541 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Mko))LROKQ62Ra8moB#j- diff --git a/schematics/p8085/mezzanine_pin.txt b/schematics/p8085/mezzanine_pin.txt index dfb85125..5296230b 100644 --- a/schematics/p8085/mezzanine_pin.txt +++ b/schematics/p8085/mezzanine_pin.txt @@ -1,17 +1,17 @@ BionicP8085 (backside) _________ _____ - VCC 40| *|1 P46 X1 GND 48| *|1 GND + VCC 40| *|1 P50 X1 GND 48| *|1 GND HOLD P37 39| |2 X2 P20 47| |2 P10 HLDA P36 38| |3 RESOUT P21 46| |3 P11 CLK P47 37| |4 P44 SOD P22 45| |4 P12 #RESIN P53 36| |5 P45 SID P23 44| B |5 P13 - READY P52 35| |6 P43 TRAP P24 43| i |6 P14 + READY P52 35| |6 P35 TRAP P24 43| i |6 P14 IO/#M P55 34| P |7 P32 RST7.5 P25 42| o |7 P15 - S1 P35 33| 8 |8 P31 RST6.5 P26 41| n |8 P16 - #RD P50 32| 0 |9 P30 RST5.5 P27 40| i |9 P17 - #WR P51 31| 8 |10 P42 INTR E1 39| c |10 E0 - ALE P40 30| 5 |11 P54 #INTA P40 38| |11 P30 - S0 P34 29| A |12 P10 AD0 P41 37| C |12 P31 + S1 P41 33| 8 |8 P31 RST6.5 P26 41| n |8 P16 + #RD P42 32| 0 |9 P30 RST5.5 P27 40| i |9 P17 + #WR P43 31| 8 |10 P34 INTR E1 39| c |10 E0 + ALE P54 30| 5 |11 P46 #INTA P40 38| |11 P30 + S0 P40 29| A |12 P10 AD0 P41 37| C |12 P31 A15 P27 28| H |13 P11 AD1 P42 36| o |13 P32 A14 P26 27| |14 P12 AD2 P43 35| n |14 P33 A13 P25 26| |15 P13 AD3 P44 34| n |15 P34 diff --git a/schematics/p8085/p8085ah_bionic.toml b/schematics/p8085/p8085ah_bionic.toml index a2d7f95f..76ed1daa 100644 --- a/schematics/p8085/p8085ah_bionic.toml +++ b/schematics/p8085/p8085ah_bionic.toml @@ -3,17 +3,17 @@ name = "P8085AH" dip = 40 width = 600 - 1 = "P46, X1" + 1 = "P50, X1" 2 = ", X2" 3 = ", RESOUT" 4 = "P44, SOD" 5 = "P45, SID" - 6 = "P43, TRAP" + 6 = "P35, TRAP" 7 = "P32, RST7.5" 8 = "P31, RST6.5" 9 = "P30, RST5.5" -10 = "P42, INTR" -11 = "P54, #INTA" +10 = "P34, INTR" +11 = "P46, #INTA" 12 = "P10, AD0" 13 = "P11, AD1" 14 = "P12, AD2" @@ -31,11 +31,11 @@ width = 600 26 = "P25, A13" 27 = "P26, A14" 28 = "P27, A15" -29 = "P34, S0" -30 = "P40, ALE" -31 = "P51, #WR" -32 = "P50, #RD" -33 = "P35, S1" +29 = "P40, S0" +30 = "P54, ALE" +31 = "P43, #WR" +32 = "P42, #RD" +33 = "P41, S1" 34 = "P55, IO/#M" 35 = "P52, READY" 36 = "P53, #RESIN"