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[RISCV] Remove experimental from Vector Crypto extensions (llvm#74213)
The RISC-V vector crypto extensions have been ratified. This patch updates the Clang and LLVM support for these extensions to be non-experimental, while leaving the C intrinsics as experimental since the C intrinsics are not yet standardized. Co-authored-by: Brandon Wu <[email protected]>
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‎llvm/docs/RISCVUsage.rst‎

Lines changed: 41 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -138,12 +138,28 @@ on support follow.
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``Zks`` Supported
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``Zkt`` Supported
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``Zmmul`` Supported
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``Zvbb`` Assembly Support
142+
``Zvbc`` Assembly Support
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``Zve32x`` (`Partially <#riscv-vlen-32-note>`__) Supported
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``Zve32f`` (`Partially <#riscv-vlen-32-note>`__) Supported
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``Zve64x`` Supported
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``Zve64f`` Supported
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``Zve64d`` Supported
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``Zvfh`` Supported
149+
``Zvkb`` Assembly Support
150+
``Zvkg`` Assembly Support
151+
``Zvkn`` Assembly Support
152+
``Zvknc`` Assembly Support
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``Zvkned`` Assembly Support
154+
``Zvkng`` Assembly Support
155+
``Zvknha`` Assembly Support
156+
``Zvknhb`` Assembly Support
157+
``Zvks`` Assembly Support
158+
``Zvksc`` Assembly Support
159+
``Zvksed`` Assembly Support
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``Zvksg`` Assembly Support
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``Zvksh`` Assembly Support
162+
``Zvkt`` Assembly Support
147163
``Zvl32b`` (`Partially <#riscv-vlen-32-note>`__) Supported
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``Zvl64b`` Supported
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``Zvl128b`` Supported
@@ -203,9 +219,6 @@ The primary goal of experimental support is to assist in the process of ratifica
203219
``experimental-ztso``
204220
LLVM implements the `v0.1 proposed specification <https://github.com/riscv/riscv-isa-manual/releases/download/draft-20220723-10eea63/riscv-spec.pdf>`__ (see Chapter 25). The mapping from the C/C++ memory model to Ztso has not yet been ratified in any standards document. There are multiple possible mappings, and they are *not* mutually ABI compatible. The mapping LLVM implements is ABI compatible with the default WMO mapping. This mapping may change and there is *explicitly* no ABI stability offered while the extension remains in experimental status. User beware.
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206-
``experimental-zvbb``, ``experimental-zvbc``, ``experimental-zvkb``, ``experimental-zvkg``, ``experimental-zvkn``, ``experimental-zvknc``, ``experimental-zvkned``, ``experimental-zvkng``, ``experimental-zvknha``, ``experimental-zvknhb``, ``experimental-zvks``, ``experimental-zvksc``, ``experimental-zvksed``, ``experimental-zvksg``, ``experimental-zvksh``, ``experimental-zvkt``
207-
LLVM implements the `1.0.0-rc2 specification <https://github.com/riscv/riscv-crypto/releases/download/v/riscv-crypto-spec-vector.pdf>`__. Note that current vector crypto extension version can be found in: <https://github.com/riscv/riscv-crypto>.
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To use an experimental extension from `clang`, you must add `-menable-experimental-extensions` to the command line, and specify the exact version of the experimental extension you are using. To use an experimental extension with LLVM's internal developer tools (e.g. `llc`, `llvm-objdump`, `llvm-mc`), you must prefix the extension name with `experimental-`. Note that you don't need to specify the version with internal tools, and shouldn't include the `experimental-` prefix with `clang`.
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211224
Vendor Extensions
@@ -266,3 +279,28 @@ The current vendor extensions supported are:
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267280
``XSfcie``
268281
LLVM implements `version 1.0.0 of the SiFive Custom Instruction Extension (CIE) Software Specification <https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf>`_ by SiFive. All custom instruction are added as described in the specification, and the riscv-toolchain-convention document linked above. These instructions are only available for S76 processor at this time.
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Experimental C Intrinsics
284+
=========================
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In some cases an extension is non-experimental but the C intrinsics for that
287+
extension are still experimental. To use C intrinsics for such an extension
288+
from `clang`, you must add `-menable-experimental-extensions` to the command
289+
line. This currently applies to the following extensions:
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291+
* ``Zvbb``
292+
* ``Zvbc``
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* ``Zvkb``
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* ``Zvkg``
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* ``Zvkn``
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* ``Zvknc``
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* ``Zvkned``
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* ``Zvkng``
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* ``Zvknha``
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* ``Zvknhb``
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* ``Zvks``
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* ``Zvksc``
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* ``Zvksed``
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* ``Zvksg``
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* ``Zvksh``
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* ``Zvkt``

‎llvm/docs/ReleaseNotes.rst‎

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@@ -338,6 +338,11 @@ Changes to the RISC-V Backend
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* CodeGen of RV32E/RV64E are supported.
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* CodeGen of ilp32e/lp64e are supported.
340340
* The Zfa extension version was upgraded to 1.0 and is no longer experimental.
341+
* The Zvbb, Zvbc, Zvkb, Zvkg, Zvkn, Zvknc, Zvkned, Zvkng, Zvknha, Zvknhb, Zvks,
342+
Zvksc, Zvksed, Zvksg, Zvksh, and Zvkt extension version was upgraded to 1.0
343+
and is no longer experimental. However, the C intrinsics for these extensions
344+
are still experimental. To use the C intrinsics for these extensions,
345+
``-menable-experimental-extensions`` needs to be passed to Clang.
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342347
Changes to the WebAssembly Backend
343348
----------------------------------

‎llvm/lib/Support/RISCVISAInfo.cpp‎

Lines changed: 19 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -147,6 +147,9 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
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148148
{"zmmul", RISCVExtensionVersion{1, 0}},
149149

150+
{"zvbb", RISCVExtensionVersion{1, 0}},
151+
{"zvbc", RISCVExtensionVersion{1, 0}},
152+
150153
{"zve32f", RISCVExtensionVersion{1, 0}},
151154
{"zve32x", RISCVExtensionVersion{1, 0}},
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{"zve64d", RISCVExtensionVersion{1, 0}},
@@ -156,6 +159,22 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
156159
{"zvfh", RISCVExtensionVersion{1, 0}},
157160
{"zvfhmin", RISCVExtensionVersion{1, 0}},
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162+
// vector crypto
163+
{"zvkb", RISCVExtensionVersion{1, 0}},
164+
{"zvkg", RISCVExtensionVersion{1, 0}},
165+
{"zvkn", RISCVExtensionVersion{1, 0}},
166+
{"zvknc", RISCVExtensionVersion{1, 0}},
167+
{"zvkned", RISCVExtensionVersion{1, 0}},
168+
{"zvkng", RISCVExtensionVersion{1, 0}},
169+
{"zvknha", RISCVExtensionVersion{1, 0}},
170+
{"zvknhb", RISCVExtensionVersion{1, 0}},
171+
{"zvks", RISCVExtensionVersion{1, 0}},
172+
{"zvksc", RISCVExtensionVersion{1, 0}},
173+
{"zvksed", RISCVExtensionVersion{1, 0}},
174+
{"zvksg", RISCVExtensionVersion{1, 0}},
175+
{"zvksh", RISCVExtensionVersion{1, 0}},
176+
{"zvkt", RISCVExtensionVersion{1, 0}},
177+
159178
{"zvl1024b", RISCVExtensionVersion{1, 0}},
160179
{"zvl128b", RISCVExtensionVersion{1, 0}},
161180
{"zvl16384b", RISCVExtensionVersion{1, 0}},
@@ -190,27 +209,9 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
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191210
{"ztso", RISCVExtensionVersion{0, 1}},
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193-
{"zvbb", RISCVExtensionVersion{1, 0}},
194-
{"zvbc", RISCVExtensionVersion{1, 0}},
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196213
{"zvfbfmin", RISCVExtensionVersion{1, 0}},
197214
{"zvfbfwma", RISCVExtensionVersion{1, 0}},
198-
199-
// vector crypto
200-
{"zvkb", RISCVExtensionVersion{1, 0}},
201-
{"zvkg", RISCVExtensionVersion{1, 0}},
202-
{"zvkn", RISCVExtensionVersion{1, 0}},
203-
{"zvknc", RISCVExtensionVersion{1, 0}},
204-
{"zvkned", RISCVExtensionVersion{1, 0}},
205-
{"zvkng", RISCVExtensionVersion{1, 0}},
206-
{"zvknha", RISCVExtensionVersion{1, 0}},
207-
{"zvknhb", RISCVExtensionVersion{1, 0}},
208-
{"zvks", RISCVExtensionVersion{1, 0}},
209-
{"zvksc", RISCVExtensionVersion{1, 0}},
210-
{"zvksed", RISCVExtensionVersion{1, 0}},
211-
{"zvksg", RISCVExtensionVersion{1, 0}},
212-
{"zvksh", RISCVExtensionVersion{1, 0}},
213-
{"zvkt", RISCVExtensionVersion{1, 0}},
214215
};
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216217
static void verifyTables() {

‎llvm/lib/Target/RISCV/RISCVFeatures.td‎

Lines changed: 20 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -607,107 +607,107 @@ def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">,
607607
"'Zawrs' (Wait on Reservation Set)">;
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609609
def FeatureStdExtZvkb
610-
: SubtargetFeature<"experimental-zvkb", "HasStdExtZvkb", "true",
610+
: SubtargetFeature<"zvkb", "HasStdExtZvkb", "true",
611611
"'Zvkb' (Vector Bit-manipulation used in Cryptography)">;
612612
def HasStdExtZvkb : Predicate<"Subtarget->hasStdExtZvkb()">,
613613
AssemblerPredicate<(all_of FeatureStdExtZvkb),
614614
"'Zvkb' (Vector Bit-manipulation used in Cryptography)">;
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616616
def FeatureStdExtZvbb
617-
: SubtargetFeature<"experimental-zvbb", "HasStdExtZvbb", "true",
617+
: SubtargetFeature<"zvbb", "HasStdExtZvbb", "true",
618618
"'Zvbb' (Vector basic bit-manipulation instructions.)",
619619
[FeatureStdExtZvkb]>;
620620
def HasStdExtZvbb : Predicate<"Subtarget->hasStdExtZvbb()">,
621621
AssemblerPredicate<(all_of FeatureStdExtZvbb),
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"'Zvbb' (Vector basic bit-manipulation instructions.)">;
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624624
def FeatureStdExtZvbc
625-
: SubtargetFeature<"experimental-zvbc", "HasStdExtZvbc", "true",
625+
: SubtargetFeature<"zvbc", "HasStdExtZvbc", "true",
626626
"'Zvbc' (Vector Carryless Multiplication)">;
627627
def HasStdExtZvbc : Predicate<"Subtarget->hasStdExtZvbc()">,
628628
AssemblerPredicate<(all_of FeatureStdExtZvbc),
629629
"'Zvbc' (Vector Carryless Multiplication)">;
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631631
def FeatureStdExtZvkg
632-
: SubtargetFeature<"experimental-zvkg", "HasStdExtZvkg", "true",
632+
: SubtargetFeature<"zvkg", "HasStdExtZvkg", "true",
633633
"'Zvkg' (Vector GCM instructions for Cryptography)">;
634634
def HasStdExtZvkg : Predicate<"Subtarget->hasStdExtZvkg()">,
635635
AssemblerPredicate<(all_of FeatureStdExtZvkg),
636636
"'Zvkg' (Vector GCM instructions for Cryptography)">;
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638638
def FeatureStdExtZvkned
639-
: SubtargetFeature<"experimental-zvkned", "HasStdExtZvkned", "true",
639+
: SubtargetFeature<"zvkned", "HasStdExtZvkned", "true",
640640
"'Zvkned' (Vector AES Encryption & Decryption (Single Round))">;
641641
def HasStdExtZvkned : Predicate<"Subtarget->hasStdExtZvkned()">,
642642
AssemblerPredicate<(all_of FeatureStdExtZvkned),
643643
"'Zvkned' (Vector AES Encryption & Decryption (Single Round))">;
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645645
def FeatureStdExtZvknha
646-
: SubtargetFeature<"experimental-zvknha", "HasStdExtZvknha", "true",
646+
: SubtargetFeature<"zvknha", "HasStdExtZvknha", "true",
647647
"'Zvknha' (Vector SHA-2 (SHA-256 only))">;
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649649
def FeatureStdExtZvknhb
650-
: SubtargetFeature<"experimental-zvknhb", "HasStdExtZvknhb", "true",
650+
: SubtargetFeature<"zvknhb", "HasStdExtZvknhb", "true",
651651
"'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))",
652652
[FeatureStdExtZvknha]>;
653653
def HasStdExtZvknha : Predicate<"Subtarget->hasStdExtZvknha()">,
654654
AssemblerPredicate<(all_of FeatureStdExtZvknha),
655655
"'Zvknha' (Vector SHA-2 (SHA-256 only))">;
656656

657657
def FeatureStdExtZvksed
658-
: SubtargetFeature<"experimental-zvksed", "HasStdExtZvksed", "true",
658+
: SubtargetFeature<"zvksed", "HasStdExtZvksed", "true",
659659
"'Zvksed' (SM4 Block Cipher Instructions)">;
660660
def HasStdExtZvksed : Predicate<"Subtarget->hasStdExtZvksed()">,
661661
AssemblerPredicate<(all_of FeatureStdExtZvksed),
662662
"'Zvksed' (SM4 Block Cipher Instructions)">;
663663

664664
def FeatureStdExtZvksh
665-
: SubtargetFeature<"experimental-zvksh", "HasStdExtZvksh", "true",
665+
: SubtargetFeature<"zvksh", "HasStdExtZvksh", "true",
666666
"'Zvksh' (SM3 Hash Function Instructions)">;
667667
def HasStdExtZvksh : Predicate<"Subtarget->hasStdExtZvksh()">,
668668
AssemblerPredicate<(all_of FeatureStdExtZvksh),
669669
"'Zvksh' (SM3 Hash Function Instructions)">;
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671671
def FeatureStdExtZvkt
672-
: SubtargetFeature<"experimental-zvkt", "HasStdExtZvkt", "true",
672+
: SubtargetFeature<"zvkt", "HasStdExtZvkt", "true",
673673
"'Zvkt' (Vector Data-Independent Execution Latency)">;
674674

675675
// Zvk short-hand extensions
676676

677677
def FeatureStdExtZvkn
678-
: SubtargetFeature<"experimental-zvkn", "HasStdExtZvkn", "true",
678+
: SubtargetFeature<"zvkn", "HasStdExtZvkn", "true",
679679
"This extension is shorthand for the following set of "
680680
"other extensions: Zvkned, Zvknhb, Zvkb and Zvkt.",
681681
[FeatureStdExtZvkned, FeatureStdExtZvknhb,
682682
FeatureStdExtZvkb, FeatureStdExtZvkt]>;
683683

684684
def FeatureStdExtZvknc
685-
: SubtargetFeature<"experimental-zvknc", "HasStdExtZvknc", "true",
685+
: SubtargetFeature<"zvknc", "HasStdExtZvknc", "true",
686686
"This extension is shorthand for the following set of "
687687
"other extensions: Zvkn and Zvbc.",
688688
[FeatureStdExtZvkn, FeatureStdExtZvbc]>;
689689

690690
def FeatureStdExtZvkng
691-
: SubtargetFeature<"experimental-zvkng", "HasStdExtZvkng", "true",
691+
: SubtargetFeature<"zvkng", "HasStdExtZvkng", "true",
692692
"This extension is shorthand for the following set of "
693693
"other extensions: Zvkn and Zvkg.",
694694
[FeatureStdExtZvkn, FeatureStdExtZvkg]>;
695695

696696
def FeatureStdExtZvks
697-
: SubtargetFeature<"experimental-zvks", "HasStdExtZvks", "true",
697+
: SubtargetFeature<"zvks", "HasStdExtZvks", "true",
698698
"This extension is shorthand for the following set of "
699699
"other extensions: Zvksed, Zvksh, Zvkb and Zvkt.",
700700
[FeatureStdExtZvksed, FeatureStdExtZvksh,
701701
FeatureStdExtZvkb, FeatureStdExtZvkt]>;
702702

703703
def FeatureStdExtZvksc
704-
: SubtargetFeature<"experimental-zvksc", "HasStdExtZvksc", "true",
704+
: SubtargetFeature<"zvksc", "HasStdExtZvksc", "true",
705705
"This extension is shorthand for the following set of "
706706
"other extensions: Zvks and Zvbc.",
707707
[FeatureStdExtZvks, FeatureStdExtZvbc]>;
708708

709709
def FeatureStdExtZvksg
710-
: SubtargetFeature<"experimental-zvksg", "HasStdExtZvksg", "true",
710+
: SubtargetFeature<"zvksg", "HasStdExtZvksg", "true",
711711
"This extension is shorthand for the following set of "
712712
"other extensions: Zvks and Zvkg.",
713713
[FeatureStdExtZvks, FeatureStdExtZvkg]>;
@@ -975,6 +975,10 @@ def TuneNoOptimizedZeroStrideLoad
975975
"false", "Hasn't optimized (perform fewer memory operations)"
976976
"zero-stride vector load">;
977977

978+
def Experimental
979+
: SubtargetFeature<"experimental", "HasExperimental",
980+
"true", "Experimental intrinsics">;
981+
978982
// Some vector hardware implementations do not process all VLEN bits in parallel
979983
// and instead split over multiple cycles. DLEN refers to the datapath width
980984
// that can be done in parallel.

‎llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td‎

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@@ -7,7 +7,7 @@
77
//===----------------------------------------------------------------------===//
88
//
99
// This file describes the RISC-V instructions from the standard 'Zvk',
10-
// Vector Cryptography Instructions extension, version 1.0.0-rc1.
10+
// Vector Cryptography Instructions extension, version Release 1.0.0.
1111
//
1212
//===----------------------------------------------------------------------===//
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