Add force-amo feature (portable_atomic_force_amo cfg)

.github/.cspell/project-dictionary.txt

@@ -4,6 +4,7 @@ alcgr
 algr
 allnoconfig
 aosp
+aqrl
 armasm
 armreg
 Auxinfo
@@ -79,10 +80,12 @@ lqarx
 lrcpc
 lwsync
 machdep
+maxu
 mfcr
 mfence
 mgba
 midr
+minu
 mipsn
 miscompiles
 mmfr
@@ -126,8 +129,10 @@ simavr
 skiboot
 slbgr
 slgr
+sllw
 spinlock
 sreg
+srlw
 sstatus
 stdarch
 stdbool

.github/workflows/ci.yml

@@ -446,6 +446,7 @@ jobs:
       matrix:
         rust:
           - '1.64'
+          - '1.72'
           - stable
           - nightly
     runs-on: ubuntu-latest

Cargo.toml

@@ -58,9 +58,18 @@ require-cas = []
 # https://github.com/taiki-e/portable-atomic#optional-features-unsafe-assume-single-core
 unsafe-assume-single-core = []
 
+# The following are sub-features of the unsafe-assume-single-core feature and if enabled without
+# the unsafe-assume-single-core feature will result in a compile error.
+# There is no explicit "unsafe-" prefix because the user has already opted in to "unsafe" by
+# enabling the unsafe-assume-single-core feature, but misuse of these features is also usually
+# considered unsound.
+# See the interrupt module's readme for more: https://github.com/taiki-e/portable-atomic/blob/HEAD/src/imp/interrupt/README.md
+
 # For RISC-V targets, generate code for S mode to disable interrupts.
 s-mode = []
-
+# For RISC-V targets, use AMO instructions even if A-extension is disabled.
+# This feature requires Rust 1.72+.
+force-amo = []
 # For ARM targets, also disable FIQs when disabling interrupts.
 disable-fiq = []
 

build.rs

@@ -22,6 +22,8 @@ fn main() {
     println!("cargo:rustc-cfg=portable_atomic_unsafe_assume_single_core");
     #[cfg(feature = "s-mode")]
     println!("cargo:rustc-cfg=portable_atomic_s_mode");
+    #[cfg(feature = "force-amo")]
+    println!("cargo:rustc-cfg=portable_atomic_force_amo");
     #[cfg(feature = "disable-fiq")]
     println!("cargo:rustc-cfg=portable_atomic_disable_fiq");
 

src/imp/interrupt/README.md

@@ -17,10 +17,11 @@ For some targets, the implementation can be changed by explicitly enabling featu
 - On pre-v6 ARM with the `disable-fiq` feature, this disables interrupts by modifying the I (IRQ mask) bit and F (FIQ mask) bit of the CPSR.
 - On RISC-V (without A-extension), this disables interrupts by modifying the MIE (Machine Interrupt Enable) bit of the `mstatus` register.
 - On RISC-V (without A-extension) with the `s-mode` feature, this disables interrupts by modifying the SIE (Supervisor Interrupt Enable) bit of the `sstatus` register.
+- On RISC-V (without A-extension) with the `force-amo` feature, this uses AMO instructions for RMWs that have corresponding AMO instructions even if A-extension is disabled. For other RMWs, this disables interrupts as usual.
 - On MSP430, this disables interrupts by modifying the GIE (Global Interrupt Enable) bit of the status register (SR).
 - On AVR, this disables interrupts by modifying the I (Global Interrupt Enable) bit of the status register (SREG).
 - On Xtensa, this disables interrupts by modifying the PS special register.
 
-Some operations don't require disabling interrupts (loads and stores on targets except for AVR, but additionally on MSP430 `add`, `sub`, `and`, `or`, `xor`, `not`). However, when the `critical-section` feature is enabled, critical sections are taken for all atomic operations.
+Some operations don't require disabling interrupts (loads and stores on targets except for AVR, but additionally on MSP430 {8,16}-bit `add,sub,and,or,xor,not`, on RISC-V with the `force-amo` feature 32-bit(RV32)/{32,64}-bit(RV64) `swap,fetch_{add,sub,and,or,xor,not,max,min},add,sub,and,or,xor,not` and {8,16}-bit `fetch_{and,or,xor,not},and,or,xor,not`). However, when the `critical-section` feature is enabled, critical sections are taken for all atomic operations.
 
 Feel free to submit an issue if your target is not supported yet.