spi: add SPI files

Author: schoeberl

7series.txt

@@ -0,0 +1,22 @@
+
+# File: 7series.txt
+interface ftdi
+ftdi device_desc "Digilent USB Device"
+ftdi vid_pid 0x0403 0x6010
+# channel 1 does not have any functionality
+ftdi channel 0
+# just TCK TDI TDO TMS, no reset
+ftdi layout_init 0x0088 0x008b
+reset_config none
+adapter speed 10000
+
+source [find cpld/xilinx-xc7.cfg]
+source [find cpld/jtagspi.cfg]
+init
+
+puts [irscan xc7.tap 0x09]
+puts [drscan xc7.tap 32 0]  
+
+puts "Programming FPGA..."
+pld load 0 build/WildcatTop.bit
+exit

Makefile

@@ -24,5 +24,20 @@ latency:
 vcd:
 	sbt "testOnly chisel3.tests.BasicTest -- -DwriteVcd=1"
 
+synpath:
+	source /home/shared/Xilinx/Vivado/2017.4/settings64.sh
+
+HW = BitBang
+
+synth:
+	./vivado_synth.sh -t $(HW) -p xc7a100tcsg324-1 -x nexysA7.xdc -o build generated/$(HW).v
+
+cp-bit:
+	-mkdir build
+	scp masca@chipdesign1.compute.dtu.dk:~/source/wildcat/build/$(HW).bit build
+# Configure the Basys3 or NexysA7 board with open source tools
+config:
+	openocd -f 7series.txt
+
 clean:
 	git clean -fd

build.sbt

@@ -29,6 +29,8 @@ developers := List(Developer("schoeberl", "schoeberl", "martin@jopdesign.com", u
 licenses += ("BSD-2-Clause", url("https://opensource.org/licenses/BSD-2-Clause"))
 publishMavenStyle := true
 
+publishConfiguration := publishConfiguration.value.withOverwrite(true)
+
 // disable publishw ith scala version, otherwise artifact name will include scala version
 // e.g cassper_2.11
 crossPaths := false

nexysA7.xdc

@@ -0,0 +1,43 @@
+package spi
+
+import chisel.lib.uart._
+import chisel3._
+import chisel3.util._
+
+/**
+  * This is the top level to for the UART output and a test blinking LED.
+  */
+class BitBang(frequ: Int) extends Module {
+  val io = IO(new Bundle {
+    val rx = Input(Bool())
+    val tx = Output(Bool())
+    val sw = Input(UInt(4.W))
+    val led = Output(UInt(4.W))
+    val ncs = Output(Bool()) // pmod 4, ic 1
+    val miso = Input(Bool()) // pmod 3, ic 2
+    val mosi = Output(Bool()) // pmod 2, ic 5
+    val sck = Output(Bool()) // pmod 1, ic 6
+  })
+  io.led := io.sw
+
+  val tx = Module(new BufferedTx(100000000, 115200))
+  val rx = Module(new Rx(100000000, 115200))
+
+  io.tx := tx.io.txd
+  rx.io.rxd := io.rx
+
+  tx.io.channel.bits := '0'.U + io.sw
+  tx.io.channel.valid := rx.io.channel.valid
+  rx.io.channel.ready := true.B
+  val regVal = RegEnable('0'.U + rx.io.channel.bits(3, 0), rx.io.channel.valid)
+  io.led := io.miso ## regVal(2, 0)
+
+  io.sck := regVal(0)
+  io.mosi := regVal(1)
+  io.ncs := regVal(2)
+}
+
+// generate Verilog
+object BitBang extends App {
+  emitVerilog(new BitBang(100000000),  Array("--target-dir", "generated"))
+}

src/main/scala/spi/BitBang.scala

@@ -0,0 +1,16 @@
+package spi
+
+import chisel3._
+class GpioPlay extends Module {
+  val io = IO(new Bundle {
+    val din = Input(UInt(4.W))
+    val led = Output(UInt(8.W))
+  })
+
+ io.led := io.din
+
+}
+
+object GpioPlay extends App {
+  emitVerilog(new GpioPlay(), Array("--target-dir", "generated"))
+}

src/main/scala/spi/GpioPlay.scala

@@ -0,0 +1,45 @@
+# SPI
+
+Play with SPI devices.
+
+See the `Makefile` for the hardware and test targets.
+
+For running SPI simulation the two Verilog files need to be added in src/test/verilog.
+Due to copyright reasons they are not included in this repository.
+
+Pmod pinout can be found at:
+
+## Links
+
+* http://ww1.microchip.com/downloads/en/devicedoc/s71271_04.pdf
+* http://www.cypress.com/file/316661/download
+* https://ww1.microchip.com/downloads/aemDocuments/documents/MPD/ProductDocuments/DataSheets/23A102423LC1024-1-Mbit-SPI-Serial-SRAM-with-SDI-SQI-Interface-20005142.pdf
+* SRAM example: https://www.mouser.dk/datasheet/2/1127/APM_PSRAM_QSPI_APS1604M_SQR_v2_5_PKG-1954861.pdf
+* Interesting IO boards: https://www.mikroe.com/flash-2-click
+* Slave implementation: https://github.com/nandland/spi-slave/blob/master/Verilog/source/SPI_Slave.v
+
+### Simulation Models
+
+* https://github.com/YosysHQ/picorv32/blob/main/picosoc/spiflash.v
+* https://www.cypress.com/verilog/s25fl256s-verilog (results in a .exe to expand)
+    * see also: https://github.com/pulp-platform/pulp/tree/master/rtl/vip/spi_flash
+* https://www.infineon.com/cms/en/product/memories/nor-flash/semper-nor-flash-family/semper-nor-flash/?gad_source=1&gclid=Cj0KCQjwlZixBhCoARIsAIC745BlF0r2uRRUs_tH-uFewg_eQ0zYvxKVwG_Ea77YYKOk0AGSk2u4oVQaAmdSEALw_wcB&gclsrc=aw.ds#!designsupport
+
+### Other Stuff
+
+* https://www.mouser.dk/ProductDetail/Infineon-Technologies/EVAL-S25HL512T?qs=T%252BzbugeAwjiZrIcBHC%252BHKw%3D%3D&utm_source=octopart&utm_medium=aggregator&utm_campaign=727-EVAL-S25HL512T&utm_content=Infineon&_gl=1*1tqxjz0*_ga*MTA4ODI1ODYwNC4xNzEzNzg5NDgw*_ga_15W4STQT4T*MTcxMzgwNDI4MC4zLjAuMTcxMzgwNDI4MC42MC4wLjA.
+* SRAM on a PCB: https://www.mouser.dk/ProductDetail/Mikroe/MIKROE-1902?qs=mzRxyRlhVdsdV%2FIU5dBGoQ%3D%3D
+* board: https://www.mouser.dk/datasheet/2/272/sram-click-manual-v100-1487260.pdf
+* See also (new ?) Click shield versions: https://www.mikroe.com/click/storage/sram
+
+## TODO
+
+* Connect Arduino and/or ESP32
+    * https://www.mouser.lu/new/adafruit/adafruit-huzzah32-esp32-dev-boards/
+* Are there better SPI simulation models? Those working with Verilator?
+* Could this be a good example for cosimulation (UVM like?)
+* Can I boot from a microSD card, just in hardware?
+* Do bit banging via serial port to SPI on the FPGA (PMOD)
+* I can explore more SPI on the Nexys:
+    * SD micro connector
+    * Accelerometer

src/main/scala/spi/README.md

@@ -0,0 +1,107 @@
+package spi
+
+import chisel3._
+import chisel3.util._
+class SpiMaster extends Module {
+  val spi = IO (new Bundle {
+    val ncs = Output(Bool())
+    val sclk = Output(Bool())
+    val mosi = Output(Bool())
+    val miso = Input(Bool())
+  })
+  val io = IO(new Bundle {
+    val dataOut = Output(UInt(8.W))
+    val dataIn = Input(UInt(8.W))
+    val dataValid = Input(Bool())
+  })
+
+  object State extends ChiselEnum {
+    val idle, tx1, tx2, rx1, rx2 = Value
+  }
+  import State._
+  val state = RegInit(idle)
+
+  val (x, y) = Counter(true.B, 10)
+  val mosiReg = RegInit(0.U(8.W))
+  val misoReg = RegInit(0.U(8.W))
+  val bitsReg = RegInit(0.U(8.W))
+  val cntReg = RegInit(0.U(8.W))
+
+
+  spi.ncs := 1.U
+  spi.sclk := x
+  spi.mosi := mosiReg(7)
+  io.dataOut := misoReg
+
+  val JTAG_ID = 0x9f.U
+  val RDSR = 0x05.U
+  val READ = 0x03.U
+
+  switch(state) {
+    is(idle) {
+      spi.ncs := 1.U
+      spi.sclk := 0.U
+      when(true.B) {
+        state := tx1
+        bitsReg := 7.U
+        cntReg := 0.U
+        mosiReg := JTAG_ID
+      }
+    }
+    is(tx1) {
+      spi.ncs := 0.U
+      spi.sclk := 0.U
+      cntReg := cntReg + 1.U
+      when(cntReg === 3.U) {
+        state := tx2
+        cntReg := 0.U
+      }
+    }
+    is(tx2) {
+      spi.ncs := 0.U
+      spi.sclk := 1.U
+      cntReg := cntReg + 1.U
+      when(cntReg === 3.U) {
+        state := tx1
+        cntReg := 0.U
+        mosiReg := mosiReg(6, 0) ## 0.U // io.dataIn(7))
+        bitsReg := bitsReg - 1.U
+        when(bitsReg === 0.U) {
+          state := rx1
+        }
+      }
+    }
+    is(rx1) {
+      spi.ncs := 0.U
+      spi.sclk := 0.U
+      cntReg := cntReg + 1.U
+      when(cntReg === 3.U) {
+        state := rx2
+        cntReg := 0.U
+        bitsReg := bitsReg - 1.U
+        when(bitsReg === 0.U) {
+          state := rx1
+        }
+      }
+    }
+    is(rx2) {
+      spi.ncs := 0.U
+      spi.sclk := 1.U
+      cntReg := cntReg + 1.U
+      when(cntReg === 3.U) {
+        state := rx1
+        cntReg := 0.U
+        bitsReg := bitsReg - 1.U
+        // probably wrong bit order
+        misoReg := spi.miso ## misoReg(7, 1)
+        when(bitsReg === 0.U) {
+          state := idle
+        }
+      }
+    }
+  }
+}
+
+object SpiMaster extends App {
+  emitVerilog(new SpiMaster(), Array("--target-dir", "generated"))
+}

src/main/scala/spi/SpiMaster.scala

@@ -0,0 +1,88 @@
+package spi
+
+/*
+ * Test SPI.
+ *
+ * Author: Martin Schoeberl (martin@jopdesign.com)
+ * 
+ */
+
+import chisel3._
+import chisel3.util._
+import chiseltest._
+import org.scalatest.flatspec.AnyFlatSpec
+
+class s25hs512t extends HasBlackBoxPath {
+  val io = IO(new Bundle() {
+    val SI = Input(Bool())
+    val SO = Output(Bool())
+    val SCK = Input(Bool())
+    val CSNeg = Input(Bool())
+    val WPNeg = Input(Bool())
+    val RESETNeg = Input(Bool())
+    val IO3_RESETNeg = Input(Bool())
+  }
+  )
+  addPath("./src/test/verilog/s25hs512t.sv")
+}
+
+
+class s25fl256s extends HasBlackBoxPath {
+  val io = IO(new Bundle() {
+    val SI = Input(Bool())
+    val SO = Output(Bool())
+    val SCK = Input(Bool())
+    val RSTNeg = Input(Bool())
+    val CSNeg = Input(Bool())
+    val WPNeg = Input(Bool())
+    val HOLDNeg = Input(Bool())
+  }
+  )
+  addPath("./src/test/verilog/s25fl256s.v")
+}
+
+
+class TopTest extends Module {
+  val io = IO(new Bundle {
+    val dout = Output(UInt(8.W))
+  })
+
+  val ctrl = Module(new SpiMaster)
+  /*
+  val flash = Module(new s25hs512t)
+  flash.io.SI := 0.U
+  flash.io.SCK := ctrl.spi.sclk
+  flash.io.CSNeg := false.B
+  flash.io.WPNeg := true.B
+  flash.io.RESETNeg := true.B // probably !reset
+  flash.io.IO3_RESETNeg := true.B
+   */
+
+  val flash = Module(new s25fl256s)
+  flash.io.SI := ctrl.spi.mosi
+  flash.io.SCK := ctrl.spi.sclk
+  flash.io.CSNeg := ctrl.spi.ncs
+  flash.io.RSTNeg := !reset.asUInt
+  flash.io.WPNeg := true.B
+  flash.io.HOLDNeg := true.B
+  ctrl.spi.miso := flash.io.SO
+
+  ctrl.io.dataIn := 0.U
+  ctrl.io.dataValid := false.B
+
+  io.dout := ctrl.io.dataOut
+}
+class TestSpiMaster extends AnyFlatSpec with ChiselScalatestTester {
+
+  "SpiMaster" should "work" in {
+    test(new SpiMaster).withAnnotations(Seq(WriteVcdAnnotation)) { dut =>
+      dut.clock.step(20)
+    }
+  }
+
+  "TopTest" should "work" in {
+    test(new TopTest).withAnnotations(Seq(WriteVcdAnnotation, IcarusBackendAnnotation)) { dut =>
+      dut.clock.step(400)
+    }
+  }
+}