Authors:	Jason Lowe-Power

Some thoughts on this document

We want this document to be living.
- We should have the source checked in somewhere (probably in a repo next to gem5).
- We should force people to make updates when they break things.
- We should have the source for the examples checked into the gem5 repo, and have tests that run them.
It may be a good idea to add example exercises at the end of each chapter. These could be things that are good for a classroom or just good things to try out.

An outline:

Part I: Getting started

Done-ish
Developing with gem5
1. Creating a new SimObject
2. Debugging support in gem5
3. Simple event-driven model
4. Adding parameters to SimObjects
5. Creating a new MemObject with master/slave ports
6. A more complex SimObject: Simple Uniprocessor cache
7. Contributing back to gem5
  
  Style guidelines
  
  Mercurial queues
  
  Reviewboard
8. Running tests
Full system simulation
1. Introduction
2. Simple FS config file
3. Building a kernel for gem5
4. Building a disk image for gem5
5. ARM simulation
6. More on X86 simulation
Advanced gem5 usage
1. Checkpoint creation and restoring
2. ISA language
3. Using m5ops
4. Using traces
An overview of common SimObjects
1. CPUs
  
  CPU models
  
  Dynamically switching CPUs
2. Classic memory system
  
  Random note: All controllers that issue coherent requests are required to have a cache attached to them. For instance, you have to have a cache on the IOBus or else there are weird errors.
3. System
Using Ruby cache coherence model
1. Overview of Ruby
2. Ruby's cache coherence protocols
3. Ruby's network topologies
4. Writing a new protocol
5. Debugging a protocol
6. Extending the SLICC language
External projects and gem5
1. Power models
2. GPU models
3. External simulation infrastructure

.. todo::

    Add information about address ranges and interleaved address ranges.

.. todolist::

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