diff --git a/CHANGELOG.md b/CHANGELOG.md index 7f452da75..ebed0c395 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -29,6 +29,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12 | Date | Version | Comment | Ticket | |:----:|:-------:|:--------|:------:| +| 23.12.2024 | 1.10.7.9 | :warning: rework IO/peripheral address space; :sparkles: increase device size from 256 bytes to 64kB | [#1126](https://github.com/stnolting/neorv32/pull/1126) | | 22.12.2024 | 1.10.7.8 | :warning: rename CPU tuning options / generics | [#1125](https://github.com/stnolting/neorv32/pull/1125) | | 22.12.2024 | 1.10.7.7 | :warning: move clock gating switch from processor top to CPU clock; `CLOCK_GATING_EN` is now a CPU tuning option | [#1124](https://github.com/stnolting/neorv32/pull/1124) | | 21.12.2024 | 1.10.7.6 | minor rtl cleanups and optimizations | [#1123](https://github.com/stnolting/neorv32/pull/1123) | diff --git a/docs/datasheet/soc.adoc b/docs/datasheet/soc.adoc index fb1dc8f3d..1cdb73ee0 100644 --- a/docs/datasheet/soc.adoc +++ b/docs/datasheet/soc.adoc @@ -468,55 +468,47 @@ table (the channel number also corresponds to the according FIRQ priority: 0 = h === Address Space As a 32-bit architecture the NEORV32 can access a 4GB physical address space. By default, this address space is -split into six main regions. Each region provides specific _physical memory attributes_ ("PMAs") that define -the access capabilities (`rwxac`; `r` = read permission, `w` = write permission, `x` - execute permission, -`a` = atomic access support, `c` = cached CPU access, `p` = privileged access only). +split into four main regions. All accesses to "unmapped" addresses (a.k.a. "the void") are redirected to the +<<_processor_external_bus_interface_xbus>>. For example, if the internal IMEM is disabled, the accesses to the +_entire_ address space between `0x00000000` and `0x7FFFFFFF` are converted into XBUS requests. If the XBUS interface +is not enabled any access to the void will raise a bus error exception. .NEORV32 Processor Address Space (Default Configuration) image::address_space.png[900] -.The "Void" (Unmapped Addresses) -[NOTE] -All accesses to "unmapped" addresses (= "void") are redirected to the <<_processor_external_bus_interface_xbus>>. -For example, if the internal IMEM is disabled, the accesses to the _entire_ address space between `0x00000000` and -`0x7FFFFFFF` are converted into XBUS requests. If the XBUS interface is not enabled any access to the void will -raise a bus error exception. +Each region provides specific _physical memory attributes_ ("PMAs") that define the access capabilities (`rwxac`; +`r` = read access, `w` = write access, `x` - execute access, `a` = atomic access, `c` = cached CPU access). + +.Custom PMAs +[TIP] +Custom physical memory attributes enforced by the CPU's _physcial memory protection_ (<<_smpmp_isa_extension>>) +can be used to further constrain the physical memory attributes. .Main Address Regions [cols="<1,^4,^2,<7"] [options="header",grid="rows"] |======================= -| # | Region | PMAs | Description -| 1 | Internal IMEM address space | `rwxac-` | For instructions (=code) and constants; mapped to the internal <<_instruction_memory_imem>>. -| 2 | Internal DMEM address space | `rwxac-` | For application runtime data (heap, stack, etc.); mapped to the internal <<_data_memory_dmem>>). -| 3 | Memory-mapped XIP flash | `r-xac-` | Memory-mapped access to the <<_execute_in_place_module_xip>> SPI flash. -| 4 | Bootloader address space | `r-xa-p` | Read-only memory for the internal <<_bootloader_rom_bootrom>> containing the default <<_bootloader>>. -| 5 | IO/peripheral address space | `rwxa-p` | Processor-internal peripherals / IO devices. -| 6 | The "**void**" | `rwxac-` | Unmapped address space. All accesses to this region(s) are redirected to the <<_processor_external_bus_interface_xbus>> (if implemented). +| # | Region | PMAs | Description +| 1 | Internal IMEM address space | `rwxac` | For instructions / code and constants; mapped to the internal <<_instruction_memory_imem>> if implemented. +| 2 | Internal DMEM address space | `rwxac` | For application runtime data (heap, stack, etc.); mapped to the internal <<_data_memory_dmem>>) if implemented. +| 3 | Memory-mapped XIP flash | `r-xac` | Transparent memory-mapped access to an external <<_execute_in_place_module_xip>> SPI flash. +| 4 | IO/peripheral address space | `rwxa-` | Processor-internal peripherals / IO devices including the <<_bootloader_rom_bootrom>>. +| - | The "**void**" | `rwxa[c]` | Unmapped address space. All accesses to this region(s) are redirected to the <<_processor_external_bus_interface_xbus>> if implemented. |======================= -.Privileged IO and BOOTROM Access Only -[IMPORTANT] -Only privileged accesses (M-mode) to the IO/peripheral and bootloader address spaces are allowed. -If an unprivileged application tries to access this address space a bus access error exception is raised. - -.Custom PMAs -[TIP] -Custom physical memory attributes enforced by the CPU's _physcial memory protection_ (<<_smpmp_isa_extension>>) -can be used to further constrain the physical memory attributes. - :sectnums: ==== Bus System -The CPU can access all of the 32-bit address space from the instruction fetch interface and also from the data access -interface. Both CPU interfaces can be equipped with optional caches (<<_processor_internal_data_cache_dcache>> and -<<_processor_internal_instruction_cache_icache>>). The two CPU interfaces are multiplexed by a simple bus switch into -a _single processor-internal bus_. Optionally, this bus is further switched by another instance of the bus switch so the -<<_direct_memory_access_controller_dma>> controller can also access the entire address space. Accesses via the -resulting SoC bus are split by the <<_bus_gateway>> that redirects accesses to the according main address regions -(see table above). Accesses to the processor-internal IO/peripheral devices are further redirected via a -dedicated <<_io_switch>>. +The CPU provides individual interfaces for instruction fetch and data access. It can can access all of the 32-bit +address space from each of the interface. Both of them can be equipped with optional caches (<<_processor_internal_data_cache_dcache>> +and <<_processor_internal_instruction_cache_icache>>). + +The two CPU interfaces are multiplexed by a simple bus switch into a _single processor-internal bus_. Optionally, +this bus is further multiplexed by another instance of the bus switch so the <<_direct_memory_access_controller_dma>> +controller can also access the entire address space. Accesses via the resulting SoC bus are split by the <<_bus_gateway>> +that redirects accesses to the according main address regions (see table above). Accesses to the processor-internal +IO/peripheral devices are further redirected via a dedicated <<_io_switch>>. .Processor-Internal Bus Architecture image::neorv32_bus.png[1300] @@ -533,31 +525,27 @@ See sections CPU <<_architecture>> and <<_bus_interface>> for more information r :sectnums: ==== Bus Gateway -The central bus gateway serves two purposes: **redirect** core accesses to the according modules (e.g. memory accesses -vs. memory-mapped IO accesses) and **monitor** all bus transactions. The redirection of access request is based on a +The central bus gateway serves two purposes: it **redirects** accesses to the according modules (e.g. memory accesses +vs. memory-mapped IO accesses) and also **monitors** all bus transactions. The redirection of access request is based on a customizable memory map implemented via VHDL constants in the main package file (`rtl/core/neorv323_package.vhd`): .Main Address Regions Configuration in the VHDL Package File [source,vhdl] ---- -- Main Address Regions --- -constant mem_imem_base_c : std_ulogic_vector(31 downto 0) := x"00000000"; -constant mem_dmem_base_c : std_ulogic_vector(31 downto 0) := x"80000000"; -constant mem_xip_base_c : std_ulogic_vector(31 downto 0) := x"e0000000"; +constant mem_imem_base_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- IMEM size via generic +constant mem_dmem_base_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- DMEM size via generic +constant mem_xip_base_c : std_ulogic_vector(31 downto 0) := x"e0000000"; -- page (4 MSBs) only! constant mem_xip_size_c : natural := 256*1024*1024; -constant mem_boot_base_c : std_ulogic_vector(31 downto 0) := x"ffffc000"; -constant mem_boot_size_c : natural := 8*1024; -constant mem_io_base_c : std_ulogic_vector(31 downto 0) := x"ffffe000"; -constant mem_io_size_c : natural := 8*1024; +constant mem_io_base_c : std_ulogic_vector(31 downto 0) := x"ffe00000"; +constant mem_io_size_c : natural := 32*64*1024; -- = 32 * iodev_size_c ---- -Besides the delegation of bus requests the gateway also implements a bus monitor (aka "the bus keeper") that tracks all -active bus transactions to ensure _safe_ and _deterministic_ operations. - -Whenever a memory-mapped device is accessed (a real memory, a memory-mapped IO or some processor-external module) the bus -monitor starts an internal timer. The accessed module has to respond ("ACK") to the bus request within a specific -**time window**. This time window is defined by a global constant in the processor's VHDL package file -(`rtl/core/neorv323_package.vhd`). +Besides the redirecting of bus requests the gateway also implements a bus monitor (aka "the bus keeper") that tracks all +active bus transactions to ensure _safe_ and _deterministic_ operations. Whenever a memory-mapped device is accessed (a +real memory, a memory-mapped IO or some processor-external module) the bus monitor starts an internal countdown. The +accessed module has to respond ("ACK") to the bus request within a bound **time window**. This time window is defined +by a global constant in the processor's VHDL package file (`rtl/core/neorv323_package.vhd`). .Internal Bus Timeout Configuration [source,vhdl] @@ -662,12 +650,6 @@ constant base_io_slink_c : std_ulogic_vector(31 downto 0) := x"ffffec00"; constant base_io_dma_c : std_ulogic_vector(31 downto 0) := x"ffffed00"; ---- -.IO Access Latency -[IMPORTANT] -In order to shorten the critical path of the IO system, the IO switch contain a partial register stage that -buffers the address bus. Hence, accesses to the processor-internal IO region requires an additional clock cycle -to complete. - <<< // #################################################################################################################### @@ -737,30 +719,31 @@ need for an explicit initialization / executable upload. :sectnums: === Processor-Internal Modules -.Privileged IO Access Only +.Full-Word Write Accesses Only [IMPORTANT] -Only privileged accesses (M-mode) to the IO/peripheral modules are allowed. If an unprivileged application -tries to access this address space a bus access error exception is raised. +All peripheral/IO devices should only be accessed in full-word mode (i.e. 32-bit). +Byte or half-word (8/16-bit) write accesses might cause undefined behavior. -.Full-Word Write Accesses Only -[NOTE] -All peripheral/IO devices should only be written in full-word mode (i.e. 32-bit). Byte or half-word (8/16-bit) write accesses -might cause undefined behavior. +.IO Module Address Space +[IMPORTAN] +Each peripheral/IO module occupies an address space of 64kB bytes. Most devices do not fully utilize this +address space and will _mirror_ the available memory-mapped registers across the entire 64kB address space. +However, accessing memory-mapped registers other than the specified ones should be avoided. -.Writing to Read-Only Registers +.Unimplemented Modules / Address Holes [NOTE] -Unless otherwise specified, writing to registers that are listed as read-only does not trigger an exception. -The write access is simply ignored by the corresponding hardware module. +When accessing an IO device that hast not been implemented (disabled via the according generic) +or when accessing an address that is actually unused, a load/store access fault exception is raised. -.IO Module's Address Space +.Writing to Read-Only Registers [NOTE] -Each peripheral/IO module occupies an address space of 256 bytes (64 words). Most devices do not fully utilize this address -space and will simply _mirror_ the available interface registers across the entire 256 bytes of address space. +Unless otherwise specified, writing to registers that are listed as read-only does not trigger an exception +as the write access is simply ignored by the corresponding hardware module. -.Unimplemented Modules / Address Holes +.IO Access Latency [NOTE] -When accessing an IO device that hast not been implemented (disabled via the according generic) -or when accessing an address that is actually unused, a load/store access fault exception is raised. +In order to shorten the critical path of the IO system, the IO switch provides register stages for the request and +response buses.Hence, accesses to the processor-internal IO region require two additional clock cycles to complete. .Module Interrupts [NOTE] diff --git a/docs/datasheet/soc_bootrom.adoc b/docs/datasheet/soc_bootrom.adoc index 5a1f19a47..f6f93365c 100644 --- a/docs/datasheet/soc_bootrom.adoc +++ b/docs/datasheet/soc_bootrom.adoc @@ -19,10 +19,11 @@ The boot ROM contains the executable image of the default NEORV32 <<_bootloader>>. When the <<_boot_configuration>> is set to _bootloader_ mode (0) via the `BOOT_MODE_SELECT` generic, the -boot ROM is automatically enabled and the CPU boot address is automatically adjusted to the -base address of the boot ROM. +boot ROM is automatically enabled and the CPU boot address is adjusted to the base address of the boot ROM. .Bootloader Image [IMPORTANT] -The boot ROM is initialized during synthesis with the default bootloader image -(`rtl/core/neorv32_bootloader_image.vhd`). Note that the BOOTROM size is constrained to 4kB. +The bootloader ROM is initialized during synthesis with the default bootloader image +(`rtl/core/neorv32_bootloader_image.vhd`). The physical size of the ROM is automatically +adjusted to the next power of two of the image size. However, note that the BOOTROM is +constrained to a maximum size of 64kB. diff --git a/docs/datasheet/soc_cfs.adoc b/docs/datasheet/soc_cfs.adoc index 8b61f0072..09aa88af0 100644 --- a/docs/datasheet/soc_cfs.adoc +++ b/docs/datasheet/soc_cfs.adoc @@ -22,7 +22,7 @@ **Overview** The custom functions subsystem is meant for implementing custom tightly-coupled co-processors or interfaces. -IT provides up to 64 32-bit memory-mapped read/write registers (`REG`, see register map below) that can be +IT provides up to 16384 32-bit memory-mapped read/write registers (`REG`, see register map below) that can be accessed by the CPU via normal load/store operations. The actual functionality of these register has to be defined by the hardware designer. Furthermore, the CFS provides two IO conduits to implement custom on-chip or off-chip interfaces. @@ -94,9 +94,9 @@ If the CFU output signals are to be used outside the chip, it is recommended to [options="header",grid="all"] |======================= | Address | Name [C] | Bit(s) | R/W | Function -| `0xffffeb00` | `REG[0]` |`31:0` | (r)/(w) | custom CFS register 0 -| `0xffffeb04` | `REG[1]` |`31:0` | (r)/(w) | custom CFS register 1 -| ... | ... |`31:0` | (r)/(w) | ... -| `0xffffebf8` | `REG[62]` |`31:0` | (r)/(w) | custom CFS register 62 -| `0xffffebfc` | `REG[63]` |`31:0` | (r)/(w) | custom CFS register 63 +| `0xffeb0000` | `REG[0]` |`31:0` | (r)/(w) | custom CFS register 0 +| `0xffeb0004` | `REG[1]` |`31:0` | (r)/(w) | custom CFS register 1 +| ... | ... |`31:0` | (r)/(w) | ... +| `0xffebfff8` | `REG[16382]` |`31:0` | (r)/(w) | custom CFS register 16382 +| `0xffebfffc` | `REG[16383]` |`31:0` | (r)/(w) | custom CFS register 16383 |======================= diff --git a/docs/datasheet/soc_crc.adoc b/docs/datasheet/soc_crc.adoc index 71d70c285..98e63eb2d 100644 --- a/docs/datasheet/soc_crc.adoc +++ b/docs/datasheet/soc_crc.adoc @@ -63,10 +63,10 @@ and for CRC32-mode the entire 32-bit of `POLY` and `SREG` are used. [options="header",grid="all"] |======================= | Address | Name [C] | Bit(s), Name [C] | R/W | Function -.2+<| `0xffffee00` .2+<| `CTRL` <|`1:0` ^| r/w <| CRC mode select (`00` CRC8, `01`: CRC16, `10`: CRC32) +.2+<| `0xffee0000` .2+<| `CTRL` <|`1:0` ^| r/w <| CRC mode select (`00` CRC8, `01`: CRC16, `10`: CRC32) <|`31:2` ^| r/- <| _reserved_, read as zero -| `0xffffee04` | `POLY` |`31:0` | r/w | CRC polynomial -.2+<| `0xffffee08` .2+<| `DATA` <|`7:0` ^| r/w <| data input (single byte) +| `0xffee0004` | `POLY` |`31:0` | r/w | CRC polynomial +.2+<| `0xffee0008` .2+<| `DATA` <|`7:0` ^| r/w <| data input (single byte) <|`31:8` ^| r/- <| _reserved_, read as zero, writes are ignored -| `0xffffee0c` | `SREG` |`32:0` | r/w | current CRC shift register value (set start value on write) +| `0xffee000c` | `SREG` |`32:0` | r/w | current CRC shift register value (set start value on write) |======================= diff --git a/docs/datasheet/soc_dma.adoc b/docs/datasheet/soc_dma.adoc index b2d9a321c..59de193c7 100644 --- a/docs/datasheet/soc_dma.adoc +++ b/docs/datasheet/soc_dma.adoc @@ -142,7 +142,7 @@ register). [options="header",grid="all"] |======================= | Address | Name [C] | Bit(s), Name [C] | R/W | Function -.12+<| `0xffffed00` .12+<| `CTRL` <|`0` `DMA_CTRL_EN` ^| r/w <| DMA module enable +.12+<| `0xffed0000` .12+<| `CTRL` <|`0` `DMA_CTRL_EN` ^| r/w <| DMA module enable <|`1` `DMA_CTRL_AUTO` ^| r/w <| Enable automatic mode (FIRQ-triggered) <|`2` `DMA_CTRL_FENCE` ^| r/w <| Issue a downstream FENCE operation when DMA transfer completes (without errors) <|`7:3` _reserved_ ^| r/- <| reserved, read as zero @@ -154,9 +154,9 @@ register). <|`15` `DMA_CTRL_FIRQ_TYPE` ^| r/w <| Trigger on rising-edge (`0`) or high-level (`1`) or selected FIRQ channel <|`19:16` `DMA_CTRL_FIRQ_SEL_MSB : DMA_CTRL_FIRQ_SEL_LSB` ^| r/w <| FIRQ trigger select (FIRQ0=0 ... FIRQ15=15) <|`31:20` _reserved_ ^| r/- <| reserved, read as zero -| `0xffffed04` | `SRC_BASE` |`31:0` | r/w | Source base address (shows the last-accessed source address when read) -| `0xffffed08` | `DST_BASE` |`31:0` | r/w | Destination base address (shows the last-accessed destination address when read) -.6+<| `0xffffed0c` .6+<| `TTYPE` <|`23:0` `DMA_TTYPE_NUM_MSB : DMA_TTYPE_NUM_LSB` ^| r/w <| Number of elements to transfer (shows the last-transferred element index when read) +| `0xffed0004` | `SRC_BASE` |`31:0` | r/w | Source base address (shows the last-accessed source address when read) +| `0xffed0008` | `DST_BASE` |`31:0` | r/w | Destination base address (shows the last-accessed destination address when read) +.6+<| `0xffed000c` .6+<| `TTYPE` <|`23:0` `DMA_TTYPE_NUM_MSB : DMA_TTYPE_NUM_LSB` ^| r/w <| Number of elements to transfer (shows the last-transferred element index when read) <|`26:24` _reserved_ ^| r/- <| reserved, read as zero <|`28:27` `DMA_TTYPE_QSEL_MSB : DMA_TTYPE_QSEL_LSB` ^| r/w <| Quantity select (`00` = byte -> byte, `01` = byte -> zero-extended-word, `10` = byte -> sign-extended-word, `11` = word -> word) <|`29` `DMA_TTYPE_SRC_INC` ^| r/w <| Constant (`0`) or incrementing (`1`) source address diff --git a/docs/datasheet/soc_gpio.adoc b/docs/datasheet/soc_gpio.adoc index 2efebce04..21e58f47d 100644 --- a/docs/datasheet/soc_gpio.adoc +++ b/docs/datasheet/soc_gpio.adoc @@ -41,8 +41,8 @@ be performed within a single clock cycle. [options="header",grid="rows"] |======================= | Address | Name [C] | Bit(s) | R/W | Function -| `0xfffffc00` | `INPUT[0]` | 31:0 | r/- | parallel input port pins 31:0 -| `0xfffffc04` | `INPUT[1]` | 31:0 | r/- | parallel input port pins 63:32 -| `0xfffffc08` | `OUTPUT[0]` | 31:0 | r/w | parallel output port pins 31:0 -| `0xfffffc0c` | `OUTPUT[1]` | 31:0 | r/w | parallel output port pins 63:32 +| `0xfffc0000` | `INPUT[0]` | 31:0 | r/- | parallel input port pins 31:0 +| `0xfffc0004` | `INPUT[1]` | 31:0 | r/- | parallel input port pins 63:32 +| `0xfffc0008` | `OUTPUT[0]` | 31:0 | r/w | parallel output port pins 31:0 +| `0xfffc000c` | `OUTPUT[1]` | 31:0 | r/w | parallel output port pins 63:32 |======================= diff --git a/docs/datasheet/soc_gptmr.adoc b/docs/datasheet/soc_gptmr.adoc index 207c50a12..7edb76a87 100644 --- a/docs/datasheet/soc_gptmr.adoc +++ b/docs/datasheet/soc_gptmr.adoc @@ -62,12 +62,12 @@ stay pending until explicitly cleared by writing a 1 to `GPTMR_CTRL_IRQ_CLR`. [options="header",grid="all"] |======================= | Address | Name [C] | Bit(s), Name [C] | R/W | Function -.6+<| `0xfffff100` .6+<| `CTRL` <|`0` `GPTMR_CTRL_EN` ^| r/w <| Timer enable flag +.6+<| `0xfff10000` .6+<| `CTRL` <|`0` `GPTMR_CTRL_EN` ^| r/w <| Timer enable flag <|`3:1` `GPTMR_CTRL_PRSC2 : GPTMR_CTRL_PRSC0` ^| r/w <| 3-bit clock prescaler select <|`4` `GPTMR_CTRL_MODE` ^| r/w <| Operation mode (0=single-shot, 1=continuous) <|`29:5` - ^| r/- <| _reserved_, read as zero <|`30` `GPTMR_CTRL_IRQ_CLR` ^| -/w <| Write `1` to clear timer-match interrupt; auto-clears <|`31` `GPTMR_CTRL_IRQ_PND` ^| r/- <| Timer-match interrupt pending -| `0xfffff104` | `THRES` |`31:0` | r/w | Threshold value register -| `0xfffff108` | `COUNT` |`31:0` | r/- | Counter register +| `0xfff10004` | `THRES` |`31:0` | r/w | Threshold value register +| `0xfff10008` | `COUNT` |`31:0` | r/- | Counter register |======================= diff --git a/docs/datasheet/soc_mtime.adoc b/docs/datasheet/soc_mtime.adoc index 5ac67c1de..bbe541ad9 100644 --- a/docs/datasheet/soc_mtime.adoc +++ b/docs/datasheet/soc_mtime.adoc @@ -45,8 +45,8 @@ high until the interrupt request is explicitly acknowledged (e.g. writing to a u [options="header",grid="all"] |======================= | Address | Name [C] | Bits | R/W | Function -| `0xfffff400` | `TIME_LO` | 31:0 | r/w | system time, low word -| `0xfffff404` | `TIME_HI` | 31:0 | r/w | system time, high word -| `0xfffff408` | `TIMECMP_LO` | 31:0 | r/w | time compare, low word -| `0xfffff40c` | `TIMECMP_HI` | 31:0 | r/w | time compare, high word +| `0xfff40000` | `TIME_LO` | 31:0 | r/w | system time, low word +| `0xfff40004` | `TIME_HI` | 31:0 | r/w | system time, high word +| `0xfff40008` | `TIMECMP_LO` | 31:0 | r/w | time compare, low word +| `0xfff4000c` | `TIMECMP_HI` | 31:0 | r/w | time compare, high word |======================= diff --git a/docs/datasheet/soc_neoled.adoc b/docs/datasheet/soc_neoled.adoc index 037055c09..353d39a08 100644 --- a/docs/datasheet/soc_neoled.adoc +++ b/docs/datasheet/soc_neoled.adoc @@ -186,7 +186,7 @@ Once the NEOLED interrupt has fired it remains pending until the actual cause of [options="header",grid="all"] |======================= | Address | Name [C] | Bit(s), Name [C] | R/W | Function -.13+<| `0xfffffd00` .13+<| `CTRL` <|`0` `NEOLED_CTRL_EN` ^| r/w <| NEOLED enable +.13+<| `0xfffd0000` .13+<| `CTRL` <|`0` `NEOLED_CTRL_EN` ^| r/w <| NEOLED enable <|`1` `NEOLED_CTRL_MODE` ^| r/w <| data transfer size; `0`=24-bit; `1`=32-bit <|`2` `NEOLED_CTRL_STROBE` ^| r/w <| `0`=send normal color data; `1`=send RESET command on data write access <|`5:3` `NEOLED_CTRL_PRSC2 : NEOLED_CTRL_PRSC0` ^| r/w <| 3-bit clock prescaler, bit 0 @@ -199,5 +199,5 @@ Once the NEOLED interrupt has fired it remains pending until the actual cause of <|`29` `NEOLED_CTRL_TX_HALF` ^| r/- <| TX FIFO is _at least_ half full <|`30` `NEOLED_CTRL_TX_FULL` ^| r/- <| TX FIFO is full <|`31` `NEOLED_CTRL_TX_BUSY` ^| r/- <| TX serial engine is busy when set -| `0xfffffd04` | `DATA` <|`31:0` / `23:0` ^| -/w <| TX data (32- or 24-bit, depending on _NEOLED_CTRL_MODE_ bit) +| `0xfffd0004` | `DATA` <|`31:0` / `23:0` ^| -/w <| TX data (32- or 24-bit, depending on _NEOLED_CTRL_MODE_ bit) |======================= diff --git a/docs/datasheet/soc_onewire.adoc b/docs/datasheet/soc_onewire.adoc index 4d2bc5f51..e5f989c6f 100644 --- a/docs/datasheet/soc_onewire.adoc +++ b/docs/datasheet/soc_onewire.adoc @@ -183,7 +183,7 @@ controller is idle (again) and the data/command FIFO is empty, the interrupt bec [options="header",grid="all"] |======================= | Address | Name [C] | Bit(s), Name [C] | R/W | Function -.11+<| `0xfffff200` .11+<| `CTRL` <|`0` `ONEWIRE_CTRL_EN` ^| r/w <| ONEWIRE enable, reset if cleared +.11+<| `0xfff20000` .11+<| `CTRL` <|`0` `ONEWIRE_CTRL_EN` ^| r/w <| ONEWIRE enable, reset if cleared <|`1` `ONEWIRE_CTRL_CLEAR` ^| -/w <| clear RXT FIFO, auto-clears <|`3:2` `ONEWIRE_CTRL_PRSC1 : ONEWIRE_CTRL_PRSC0` ^| r/w <| 2-bit clock prescaler select <|`11:4` `ONEWIRE_CTRL_CLKDIV7 : ONEWIRE_CTRL_CLKDIV0` ^| r/w <| 8-bit clock divider value @@ -194,7 +194,7 @@ controller is idle (again) and the data/command FIFO is empty, the interrupt bec <|`29` `ONEWIRE_CTRL_RX_AVAIL` ^| r/- <| RX FIFO data available <|`30` `ONEWIRE_CTRL_SENSE` ^| r/- <| current state of the bus line <|`31` `ONEWIRE_CTRL_BUSY` ^| r/- <| operation in progress when set or TX FIFO not empty -.4+<| `0xfffff204` .4+<| `DCMD` <|`7:0` `ONEWIRE_DCMD_DATA_MSB : ONEWIRE_DCMD_DATA_LSB` ^| r/w <| receive/transmit data +.4+<| `0xfff20004` .4+<| `DCMD` <|`7:0` `ONEWIRE_DCMD_DATA_MSB : ONEWIRE_DCMD_DATA_LSB` ^| r/w <| receive/transmit data <|`9:8` `ONEWIRE_DCMD_CMD_HI : ONEWIRE_DCMD_CMD_LO` ^| -/w <| operation command LSBs <|`10` `ONEWIRE_DCMD_PRESENCE` ^| -/w <| bus presence detected <|`31:11` - ^| r/- <| _reserved_, read as zero diff --git a/docs/datasheet/soc_pwm.adoc b/docs/datasheet/soc_pwm.adoc index 09d9ac687..9ecb9199d 100644 --- a/docs/datasheet/soc_pwm.adoc +++ b/docs/datasheet/soc_pwm.adoc @@ -60,18 +60,18 @@ _f~PWM~_[Hz] = _f~main~_[Hz] / (2^8^ * `clock_prescaler` * (1 + `PWM_CFG_CDIV`)) **Register Map** -.PWM register map (`struct neorv32_pwm_t`) +.PWM register map (`struct NEORV32_PWM`) [cols="<4,<2,<6,^2,<8"] [options="header",grid="all"] |======================= | Address | Name [C] | Bit(s), Name [C] | R/W | Function -.5+<| `0xfffff000` .5+<| `CHANNEL_CFG[0]` <|`31` - `PWM_CFG_EN` ^| r/w <| Channel 0: channel enabled when set +.5+<| `0xfff00000` .5+<| `CHANNEL_CFG[0]` <|`31` - `PWM_CFG_EN` ^| r/w <| Channel 0: channel enabled when set <|`30:28` - `PWM_CFG_PRSC_MSB:PWM_CFG_PRSC_LSB` ^| r/w <| Channel 0: 3-bit clock prescaler select <|`27:18` ^| r/- <| Channel 0: _reserved_, hardwired to zero <|`17:8` - `PWM_CFG_CDIV_MSB:PWM_CFG_CDIV_LSB` ^| r/w <| Channel 0: 10-bit clock divider <|`7:0` - `PWM_CFG_DUTY_MSB:PWM_CFG_DUTY_LSB` ^| r/w <| Channel 0: 8-bit duty cycle -| `0xfffff004` ... `0xfffff038` | `CHANNEL_CFG[1]` ... `CHANNEL_CFG[14]` | ... | r/w <| Channels 1 to 14 -.5+<| `0xfffff03C` .5+<| `CHANNEL_CFG[15]` <|`31` - `PWM_CFG_EN` ^| r/w <| Channel 15: channel enabled when set +| `0xfff00004` ... `0xfff00038` | `CHANNEL_CFG[1]` ... `CHANNEL_CFG[14]` | ... | r/w <| Channels 1 to 14 +.5+<| `0xfff0003C` .5+<| `CHANNEL_CFG[15]` <|`31` - `PWM_CFG_EN` ^| r/w <| Channel 15: channel enabled when set <|`30:28` - `PWM_CFG_PRSC_MSB:PWM_CFG_PRSC_LSB` ^| r/w <| Channel 15: 3-bit clock prescaler select <|`27:18` ^| r/- <| Channel 15: _reserved_, hardwired to zero <|`17:8` - `PWM_CFG_CDIV_MSB:PWM_CFG_CDIV_LSB` ^| r/w <| Channel 15: 10-bit clock divider diff --git a/docs/datasheet/soc_sdi.adoc b/docs/datasheet/soc_sdi.adoc index cfdac40e8..fe4c4669f 100644 --- a/docs/datasheet/soc_sdi.adoc +++ b/docs/datasheet/soc_sdi.adoc @@ -87,7 +87,7 @@ example if just the `SDI_CTRL_IRQ_RX_AVAIL` bit is set, the interrupt will keep [options="header",grid="all"] |======================= | Address | Name [C] | Bit(s), Name [C] | R/W | Function -.18+<| `0xfffff700` .18+<| `CTRL` <|`0` `SDI_CTRL_EN` ^| r/w <| SDI module enable +.18+<| `0xfff70000` .18+<| `CTRL` <|`0` `SDI_CTRL_EN` ^| r/w <| SDI module enable <|`3:1` _reserved_ ^| r/- <| reserved, read as zero <|`7:4` `SDI_CTRL_FIFO_MSB : SDI_CTRL_FIFO_LSB` ^| r/- <| FIFO depth; log2(_IO_SDI_FIFO_) <|`14:8` _reserved_ ^| r/- <| reserved, read as zero @@ -105,6 +105,6 @@ example if just the `SDI_CTRL_IRQ_RX_AVAIL` bit is set, the interrupt will keep <|`28` `SDI_CTRL_TX_FULL` ^| r/- <| TX FIFO full <|`30:29` _reserved_ ^| r/- <| reserved, read as zero <|`31` `SDI_CTRL_CS_ACTIVE` ^| r/- <| Chip-select is active when set -.2+<| `0xfffff704` .2+<| `DATA` <|`7:0` ^| r/w <| receive/transmit data (FIFO) +.2+<| `0xfff70004` .2+<| `DATA` <|`7:0` ^| r/w <| receive/transmit data (FIFO) <|`31:8` _reserved_ ^| r/- <| reserved, read as zero |======================= diff --git a/docs/datasheet/soc_slink.adoc b/docs/datasheet/soc_slink.adoc index 3e4e7c42e..c33d1755e 100644 --- a/docs/datasheet/soc_slink.adoc +++ b/docs/datasheet/soc_slink.adoc @@ -116,31 +116,31 @@ interrupt-causing condition is resolved (e.g. by reading from the RX FIFO). [options="header",grid="all"] |======================= | Address | Name [C] | Bit(s) | R/W | Function -.22+<| `0xffffec00` .22+<| `NEORV32_SLINK.CTRL` <| `0` `SLINK_CTRL_EN` ^| r/w <| SLINK global enable - <| `1` `SLINK_CTRL_RX_CLR` ^| -/w <| Clear RX FIFO when set (bit auto-clears) - <| `2` `SLINK_CTRL_TX_CLR` ^| -/w <| Clear TX FIFO when set (bit auto-clears) - <| `3` _reserved_ ^| r/- <| _reserved_, read as zero - <| `4` `SLINK_CTRL_RX_LAST` ^| r/- <| Last word read from `RX_DATA` is marked as "end of stream" - <| `7:5` _reserved_ ^| r/- <| _reserved_, read as zero - <| `8` `SLINK_CTRL_RX_EMPTY` ^| r/- <| RX FIFO empty - <| `9` `SLINK_CTRL_RX_HALF` ^| r/- <| RX FIFO at least half full - <| `10` `SLINK_CTRL_RX_FULL` ^| r/- <| RX FIFO full - <| `11` `SLINK_CTRL_TX_EMPTY` ^| r/- <| TX FIFO empty - <| `12` `SLINK_CTRL_TX_HALF` ^| r/- <| TX FIFO at least half full - <| `13` `SLINK_CTRL_TX_FULL` ^| r/- <| TX FIFO full - <| `15:14` _reserved_ ^| r/- <| _reserved_, read as zero - <| `16` `SLINK_CTRL_IRQ_RX_NEMPTY` ^| r/w <| RX interrupt if RX FIFO not empty - <| `17` `SLINK_CTRL_IRQ_RX_HALF` ^| r/w <| RX interrupt if RX FIFO at least half full - <| `18` `SLINK_CTRL_IRQ_RX_FULL` ^| r/w <| RX interrupt if RX FIFO full - <| `19` `SLINK_CTRL_IRQ_TX_EMPTY` ^| r/w <| TX interrupt if TX FIFO empty - <| `20` `SLINK_CTRL_IRQ_TX_NHALF` ^| r/w <| TX interrupt if TX FIFO not at least half full - <| `21` `SLINK_CTRL_IRQ_TX_NFULL` ^| r/w <| TX interrupt if TX FIFO not full - <| `23:22` _reserved_ ^| r/- <| _reserved_, read as zero - <| `27:24` `SLINK_CTRL_RX_FIFO_MSB : SLINK_CTRL_RX_FIFO_LSB` ^| r/- <| log2(RX FIFO size) - <| `31:28` `SLINK_CTRL_TX_FIFO_MSB : SLINK_CTRL_TX_FIFO_LSB` ^| r/- <| log2(TX FIFO size) -.3+<| `0xffffec04` .3+<| `NEORV32_SLINK.ROUTE` <| `3:0` | r/w | TX destination routing information (`slink_tx_dst_o`) - <| `7:4` | r/- | RX source routing information (`slink_rx_src_i`) - <| `31:8` | -/- | _reserved_ -| `0xffffec08` | `NEORV32_SLINK.DATA` | `31:0` | r/w | Write data to TX FIFO; read data from RX FIFO -| `0xffffec0c` | `NEORV32_SLINK.DATA_LAST` | `31:0` | r/w | Write data to TX FIFO (and also set "last" signal); read data from RX FIFO +.22+<| `0xffec0000` .22+<| `CTRL` <| `0` `SLINK_CTRL_EN` ^| r/w <| SLINK global enable + <| `1` `SLINK_CTRL_RX_CLR` ^| -/w <| Clear RX FIFO when set (bit auto-clears) + <| `2` `SLINK_CTRL_TX_CLR` ^| -/w <| Clear TX FIFO when set (bit auto-clears) + <| `3` _reserved_ ^| r/- <| _reserved_, read as zero + <| `4` `SLINK_CTRL_RX_LAST` ^| r/- <| Last word read from `RX_DATA` is marked as "end of stream" + <| `7:5` _reserved_ ^| r/- <| _reserved_, read as zero + <| `8` `SLINK_CTRL_RX_EMPTY` ^| r/- <| RX FIFO empty + <| `9` `SLINK_CTRL_RX_HALF` ^| r/- <| RX FIFO at least half full + <| `10` `SLINK_CTRL_RX_FULL` ^| r/- <| RX FIFO full + <| `11` `SLINK_CTRL_TX_EMPTY` ^| r/- <| TX FIFO empty + <| `12` `SLINK_CTRL_TX_HALF` ^| r/- <| TX FIFO at least half full + <| `13` `SLINK_CTRL_TX_FULL` ^| r/- <| TX FIFO full + <| `15:14` _reserved_ ^| r/- <| _reserved_, read as zero + <| `16` `SLINK_CTRL_IRQ_RX_NEMPTY` ^| r/w <| RX interrupt if RX FIFO not empty + <| `17` `SLINK_CTRL_IRQ_RX_HALF` ^| r/w <| RX interrupt if RX FIFO at least half full + <| `18` `SLINK_CTRL_IRQ_RX_FULL` ^| r/w <| RX interrupt if RX FIFO full + <| `19` `SLINK_CTRL_IRQ_TX_EMPTY` ^| r/w <| TX interrupt if TX FIFO empty + <| `20` `SLINK_CTRL_IRQ_TX_NHALF` ^| r/w <| TX interrupt if TX FIFO not at least half full + <| `21` `SLINK_CTRL_IRQ_TX_NFULL` ^| r/w <| TX interrupt if TX FIFO not full + <| `23:22` _reserved_ ^| r/- <| _reserved_, read as zero + <| `27:24` `SLINK_CTRL_RX_FIFO_MSB : SLINK_CTRL_RX_FIFO_LSB` ^| r/- <| log2(RX FIFO size) + <| `31:28` `SLINK_CTRL_TX_FIFO_MSB : SLINK_CTRL_TX_FIFO_LSB` ^| r/- <| log2(TX FIFO size) +.3+<| `0xffec0004` .3+<| `ROUTE` <| `3:0` | r/w | TX destination routing information (`slink_tx_dst_o`) + <| `7:4` | r/- | RX source routing information (`slink_rx_src_i`) + <| `31:8` | -/- | _reserved_ +| `0xffec0008` | `DATA` | `31:0` | r/w | Write data to TX FIFO; read data from RX FIFO +| `0xffec000c` | `DATA_LAST` | `31:0` | r/w | Write data to TX FIFO (and also set "last" signal); read data from RX FIFO |======================= diff --git a/docs/datasheet/soc_spi.adoc b/docs/datasheet/soc_spi.adoc index 1c45f6c9f..f20a20a4d 100644 --- a/docs/datasheet/soc_spi.adoc +++ b/docs/datasheet/soc_spi.adoc @@ -126,7 +126,7 @@ example if just the `SPI_CTRL_IRQ_RX_AVAIL` bit is set, the interrupt will keep [options="header",grid="all"] |======================= | Address | Name [C] | Bit(s), Name [C] | R/W | Function -.19+<| `0xfffff800` .19+<| `CTRL` <|`0` `SPI_CTRL_EN` ^| r/w <| SPI module enable +.19+<| `0xfff80000` .19+<| `CTRL` <|`0` `SPI_CTRL_EN` ^| r/w <| SPI module enable <|`1` `SPI_CTRL_CPHA` ^| r/w <| clock phase <|`2` `SPI_CTRL_CPOL` ^| r/w <| clock polarity <|`5:3` `SPI_CTRL_PRSC2 : SPI_CTRL_PRSC0` ^| r/w <| 3-bit clock prescaler select @@ -145,7 +145,7 @@ example if just the `SPI_CTRL_IRQ_RX_AVAIL` bit is set, the interrupt will keep <|`30:28` _reserved_ ^| r/- <| reserved, read as zero <|`30` `SPI_CS_ACTIVE` ^| r/- <| Set if any chip-select line is active <|`31` `SPI_CTRL_BUSY` ^| r/- <| SPI module busy when set (serial engine operation in progress and TX FIFO not empty yet) -.3+<| `0xfffff804` .3+<| `DATA` <|`7:0` `SPI_DATA_MSB : SPI_DATA_LSB` ^| r/w <| receive/transmit data (FIFO) +.3+<| `0xfff80004` .3+<| `DATA` <|`7:0` `SPI_DATA_MSB : SPI_DATA_LSB` ^| r/w <| receive/transmit data (FIFO) <|`30:8` _reserved_ ^| r/- <| reserved, read as zero <|`31` `SPI_DATA_CMD` ^| -/w <| data (`0`) / chip-select-command (`1`) select |======================= diff --git a/docs/datasheet/soc_sysinfo.adoc b/docs/datasheet/soc_sysinfo.adoc index f104b18e5..e4b0e455a 100644 --- a/docs/datasheet/soc_sysinfo.adoc +++ b/docs/datasheet/soc_sysinfo.adoc @@ -42,10 +42,10 @@ to take into account a dynamic frequency scaling of the processor. [options="header",grid="all"] |======================= | Address | Name [C] | R/W | Description -| `0xfffffe00` | `CLK` | r/w | clock frequency in Hz (initialized from top's `CLOCK_FREQUENCY` generic) -| `0xfffffe04` | `MEM[4]` | r/- | internal memory configuration (see <<_sysinfo_memory_configuration>>) -| `0xfffffe08` | `SOC` | r/- | specific SoC configuration (see <<_sysinfo_soc_configuration>>) -| `0xfffffe0c` | `CACHE` | r/- | cache configuration information (see <<_sysinfo_cache_configuration>>) +| `0xfffe0000` | `CLK` | r/w | clock frequency in Hz (initialized from top's `CLOCK_FREQUENCY` generic) +| `0xfffe0004` | `MEM[4]` | r/- | internal memory configuration (see <<_sysinfo_memory_configuration>>) +| `0xfffe0008` | `SOC` | r/- | specific SoC configuration (see <<_sysinfo_soc_configuration>>) +| `0xfffe000c` | `CACHE` | r/- | cache configuration information (see <<_sysinfo_cache_configuration>>) |======================= diff --git a/docs/datasheet/soc_trng.adoc b/docs/datasheet/soc_trng.adoc index bb1ef47d9..83aadbf73 100644 --- a/docs/datasheet/soc_trng.adoc +++ b/docs/datasheet/soc_trng.adoc @@ -63,11 +63,11 @@ mode is active. [options="header",grid="all"] |======================= | Address | Name [C] | Bit(s), Name [C] | R/W | Function -.5+<| `0xfffffa00` .5+<| `CTRL` <|`0` `TRNG_CTRL_EN` ^| r/w <| TRNG enable +.5+<| `0xfffa0000` .5+<| `CTRL` <|`0` `TRNG_CTRL_EN` ^| r/w <| TRNG enable <|`1` `TRNG_CTRL_FIFO_CLR` ^| -/w <| flush random data FIFO when set; flag auto-clears <|`5:2` `TRNG_CTRL_FIFO_MSB : TRNG_CTRL_FIFO_LSB` ^| r/- <| FIFO depth, log2(`IO_TRNG_FIFO`) <|`6` `TRNG_CTRL_SIM_MODE` ^| r/- <| simulation mode (PRNG!) <|`7` `TRNG_CTRL_AVAIL` ^| r/- <| random data available when set -.2+<| `0xfffffa04` .2+<| `DATA` <|`7:0` `TRNG_DATA_MSB : TRNG_DATA_LSB` ^| r/- <| random data byte +.2+<| `0xfffa0004` .2+<| `DATA` <|`7:0` `TRNG_DATA_MSB : TRNG_DATA_LSB` ^| r/- <| random data byte <|`31:8` _reserved_ ^| r/- <| reserved, read as zero |======================= diff --git a/docs/datasheet/soc_twd.adoc b/docs/datasheet/soc_twd.adoc index dd74f858f..1e0e65bea 100644 --- a/docs/datasheet/soc_twd.adoc +++ b/docs/datasheet/soc_twd.adoc @@ -144,7 +144,7 @@ twd_scl_i <= std_ulogic(scl_io); -- sense [options="header",grid="all"] |======================= | Address | Name [C] | Bit(s), Name [C] | R/W | Function -.18+<| `0xffffea00` .18+<| `CTRL` <|`0` `TWD_CTRL_EN` ^| r/w <| TWD enable, reset if cleared +.18+<| `0xffea0000` .18+<| `CTRL` <|`0` `TWD_CTRL_EN` ^| r/w <| TWD enable, reset if cleared <|`1` `TWD_CTRL_CLR_RX` ^| -/w <| Clear RX FIFO, flag auto-clears <|`2` `TWD_CTRL_CLR_TX` ^| -/w <| Clear TX FIFO, flag auto-clears <|`3` `TWD_CTRL_FSEL` ^| r/w <| Bus sample clock / filter select @@ -162,6 +162,6 @@ twd_scl_i <= std_ulogic(scl_io); -- sense <|`29` `TWD_CTRL_SENSE_SCL` ^| r/- <| current state of the SCL bus line <|`30` `TWD_CTRL_SENSE_SDA` ^| r/- <| current state of the SDA bus line <|`31` `TWD_CTRL_BUSY` ^| r/- <| bus engine is busy (transaction in progress) -.2+<| `0xffffea04` .2+<| `DATA` <|`7:0` `TWD_DATA_MSB : TWD_DATA_LSB` ^| r/w <| RX/TX data FIFO access +.2+<| `0xffea0004` .2+<| `DATA` <|`7:0` `TWD_DATA_MSB : TWD_DATA_LSB` ^| r/w <| RX/TX data FIFO access <|`31:8` - ^| r/- <| _reserved_, read as zero |======================= diff --git a/docs/datasheet/soc_twi.adoc b/docs/datasheet/soc_twi.adoc index d1e4b38cd..8fa7aa93f 100644 --- a/docs/datasheet/soc_twi.adoc +++ b/docs/datasheet/soc_twi.adoc @@ -136,7 +136,7 @@ TWI module is enabled (`TWI_CTRL_EN` = `1`) and the TX FIFO is empty and the TWI [options="header",grid="all"] |======================= | Address | Name [C] | Bit(s), Name [C] | R/W | Function -.12+<| `0xfffff900` .12+<| `CTRL` <|`0` `TWI_CTRL_EN` ^| r/w <| TWI enable, reset if cleared +.12+<| `0xfff90000` .12+<| `CTRL` <|`0` `TWI_CTRL_EN` ^| r/w <| TWI enable, reset if cleared <|`3:1` `TWI_CTRL_PRSC2 : TWI_CTRL_PRSC0` ^| r/w <| 3-bit clock prescaler select <|`7:4` `TWI_CTRL_CDIV3 : TWI_CTRL_CDIV0` ^| r/w <| 4-bit clock divider <|`8` `TWI_CTRL_CLKSTR` ^| r/w <| Enable (allow) clock stretching @@ -148,7 +148,7 @@ TWI module is enabled (`TWI_CTRL_EN` = `1`) and the TX FIFO is empty and the TWI <|`29` `TWI_CTRL_TX_FULL` ^| r/- <| set if the TWI bus is claimed by any controller <|`30` `TWI_CTRL_RX_AVAIL` ^| r/- <| RX FIFO data available <|`31` `TWI_CTRL_BUSY` ^| r/- <| TWI bus engine busy or TX FIFO not empty -.3+<| `0xfffff904` .3+<| `DCMD` <|`7:0` `TWI_DCMD_MSB : TWI_DCMD_LSB` ^| r/w <| RX/TX data byte +.3+<| `0xfff90004` .3+<| `DCMD` <|`7:0` `TWI_DCMD_MSB : TWI_DCMD_LSB` ^| r/w <| RX/TX data byte <|`8` `TWI_DCMD_ACK` ^| r/w <| write: ACK bit sent by controller; read: `1` = device NACK, `0` = device ACK <|`10:9` `TWI_DCMD_CMD_HI : TWI_DCMD_CMD_LO` ^| r/w <| TWI operation (`00` = NOP, `01` = START conditions, `10` = STOP condition, `11` = data transmission) |======================= diff --git a/docs/datasheet/soc_uart.adoc b/docs/datasheet/soc_uart.adoc index 01d62d0df..b67abbb74 100644 --- a/docs/datasheet/soc_uart.adoc +++ b/docs/datasheet/soc_uart.adoc @@ -128,7 +128,7 @@ Both file are created in the simulation's home folder. [options="header",grid="all"] |======================= | Address | Name [C] | Bit(s), Name [C] | R/W | Function -.20+<| `0xfffff500` .20+<| `CTRL` <|`0` `UART_CTRL_EN` ^| r/w <| UART enable +.21+<| `0xfff50000` .21+<| `CTRL` <|`0` `UART_CTRL_EN` ^| r/w <| UART enable <|`1` `UART_CTRL_SIM_MODE` ^| r/w <| enable **simulation mode** <|`2` `UART_CTRL_HWFC_EN` ^| r/w <| enable RTS/CTS hardware flow-control <|`5:3` `UART_CTRL_PRSC2 : UART_CTRL_PRSC0` ^| r/w <| Baud rate clock prescaler select @@ -149,7 +149,7 @@ Both file are created in the simulation's home folder. <|`29` `UART_CTRL_TX_CLR` ^| r/w <| Clear TX FIFO, flag auto-clears <|`30` `UART_CTRL_RX_OVER` ^| r/- <| RX FIFO overflow; cleared by disabling the module <|`31` `UART_CTRL_TX_BUSY` ^| r/- <| TX busy or TX FIFO not empty -.4+<| `0xfffff504` .4+<| `DATA` <|`7:0` `UART_DATA_RTX_MSB : UART_DATA_RTX_LSB` ^| r/w <| receive/transmit data +.4+<| `0xfff50004` .4+<| `DATA` <|`7:0` `UART_DATA_RTX_MSB : UART_DATA_RTX_LSB` ^| r/w <| receive/transmit data <|`11:8` `UART_DATA_RX_FIFO_SIZE_MSB : UART_DATA_RX_FIFO_SIZE_LSB` ^| r/- <| log2(RX FIFO size) <|`15:12` `UART_DATA_TX_FIFO_SIZE_MSB : UART_DATA_TX_FIFO_SIZE_LSB` ^| r/- <| log2(TX FIFO size) <|`31:16` ^| r/- <| _reserved_, read as zero @@ -202,6 +202,6 @@ written to UART1-specific file `neorv32.uart1_sim_mode.out`. This data is also p [options="header",grid="all"] |======================= | Address | Name [C] | Bit(s), Name [C] | R/W | Function -| `0xfffff600` | `CTRL` | ... | ... | Same as UART0 -| `0xfffff604` | `DATA` | ... | ... | Same as UART0 +| `0xfff60000` | `CTRL` | ... | ... | Same as UART0 +| `0xfff60004` | `DATA` | ... | ... | Same as UART0 |======================= diff --git a/docs/datasheet/soc_wdt.adoc b/docs/datasheet/soc_wdt.adoc index 0b98622cb..5e8a3d3c7 100644 --- a/docs/datasheet/soc_wdt.adoc +++ b/docs/datasheet/soc_wdt.adoc @@ -84,7 +84,7 @@ The cause of the last system hardware reset can be determined via the `WDT_CTRL_ [options="header",grid="all"] |======================= | Address | Name [C] | Bit(s), Name [C] | R/W | Reset value | Writable if locked | Function -.8+<| `0xfffffb00` .8+<| `CTRL` <|`0` `WDT_CTRL_EN` ^| r/w ^| `0` ^| no <| watchdog enable +.8+<| `0xfffb0000` .8+<| `CTRL` <|`0` `WDT_CTRL_EN` ^| r/w ^| `0` ^| no <| watchdog enable <|`1` `WDT_CTRL_LOCK` ^| r/w ^| `0` ^| no <| lock configuration when set, clears only on system reset, can only be set if enable bit is set already <|`2` `WDT_CTRL_DBEN` ^| r/w ^| `0` ^| no <| set to allow WDT to continue operation even when CPU is in debug mode <|`3` `WDT_CTRL_SEN` ^| r/w ^| `0` ^| no <| set to allow WDT to continue operation even when CPU is in sleep mode @@ -92,5 +92,5 @@ The cause of the last system hardware reset can be determined via the `WDT_CTRL_ <|`6:5` `WDT_CTRL_RCAUSE_HI : WDT_CTRL_RCAUSE_LO` ^| r/- ^| `0` ^| - <| cause of last system reset; 0=external reset, 1=ocd-reset, 2=watchdog reset <|`7` - ^| r/- ^| - ^| - <| _reserved_, reads as zero <|`31:8` `WDT_CTRL_TIMEOUT_MSB : WDT_CTRL_TIMEOUT_LSB` ^| r/w ^| 0 ^| no <| 24-bit watchdog timeout value -| `0xfffffb04` | `RESET` |`31:0` | -/w | - | yes | Write _PASSWORD_ to reset WDT timeout counter +| `0xfffb0004` | `RESET` |`31:0` | -/w | - | yes | Write _PASSWORD_ to reset WDT timeout counter |======================= diff --git a/docs/datasheet/soc_xip.adoc b/docs/datasheet/soc_xip.adoc index ec9caf4ad..6d70e7e1d 100644 --- a/docs/datasheet/soc_xip.adoc +++ b/docs/datasheet/soc_xip.adoc @@ -193,7 +193,7 @@ The XIP cache is cleared when the XIP module is disabled (`XIP_CTRL_EN = 0`), wh [options="header",grid="all"] |======================= | Address | Name [C] | Bit(s), Name [C] | R/W | Function -.14+<| `0xffffff40` .14+<| `CTRL` <|`0` `XIP_CTRL_EN` ^| r/w <| XIP module enable +.14+<| `0xffff4000` .14+<| `CTRL` <|`0` `XIP_CTRL_EN` ^| r/w <| XIP module enable <|`3:1` `XIP_CTRL_PRSC2 : XIP_CTRL_PRSC0` ^| r/w <| 3-bit SPI clock prescaler select <|`4` `XIP_CTRL_CPOL` ^| r/w <| SPI clock polarity <|`5` `XIP_CTRL_CPHA` ^| r/w <| SPI clock phase @@ -207,7 +207,7 @@ The XIP cache is cleared when the XIP module is disabled (`XIP_CTRL_EN = 0`), wh <|`29:27` - ^| r/- <| _reserved_, read as zero <|`30` `XIP_CTRL_PHY_BUSY` ^| r/- <| SPI PHY busy when set <|`31` `XIP_CTRL_XIP_BUSY` ^| r/- <| XIP access in progress when set -| `0xffffff44` | _reserved_ |`31:0` | r/- | _reserved_, read as zero -| `0xffffff48` | `DATA_LO` |`31:0` | r/w | Direct SPI access - data register low -| `0xffffff4C` | `DATA_HI` |`31:0` | -/w | Direct SPI access - data register high; write access triggers SPI transfer +| `0xffff4004` | _reserved_ |`31:0` | r/- | _reserved_, read as zero +| `0xffff4008` | `DATA_LO` |`31:0` | r/w | Direct SPI access - data register low +| `0xffff400C` | `DATA_HI` |`31:0` | -/w | Direct SPI access - data register high; write access triggers SPI transfer |======================= diff --git a/docs/datasheet/soc_xirq.adoc b/docs/datasheet/soc_xirq.adoc index 5cb97b853..844652d46 100644 --- a/docs/datasheet/soc_xirq.adoc +++ b/docs/datasheet/soc_xirq.adoc @@ -74,10 +74,10 @@ can issue a new CPU interrupt). [options="header",grid="all"] |======================= | Address | Name [C] | Bit(s) | R/W | Description -| `0xfffff300` | `EIE` | `31:0` | r/w | External interrupt enable register (one bit per channel, LSB-aligned) -.3+^| `0xfffff304` .3+<| `ESC` ^| `31` ^| r/c <| XIRQ interrupt when set; write any value to this register to acknowledge the current XIRQ interrupt +| `0xfff30000` | `EIE` | `31:0` | r/w | External interrupt enable register (one bit per channel, LSB-aligned) +.3+^| `0xfff30004` .3+<| `ESC` ^| `31` ^| r/c <| XIRQ interrupt when set; write any value to this register to acknowledge the current XIRQ interrupt ^| `30:5` ^| r/- <| _reserved_, read as zero ^| `4:0` ^| r/c <| Interrupt source ID (0..31) of firing IRQ (prioritized!) -| `0xfffff308` | `TTYP` | `31:0` | r/w | Trigger type select (`0` = level trigger, `1` = edge trigger); each bit corresponds to the according channel number -| `0xfffff30c` | `TPOL` | `31:0` | r/w | Trigger polarity select (`0` = low-level/falling-edge, `1` = high-level/rising-edge); each bit corresponds to the according channel number +| `0xfff30008` | `TTYP` | `31:0` | r/w | Trigger type select (`0` = level trigger, `1` = edge trigger); each bit corresponds to the according channel number +| `0xfff3000c` | `TPOL` | `31:0` | r/w | Trigger polarity select (`0` = low-level/falling-edge, `1` = high-level/rising-edge); each bit corresponds to the according channel number |======================= diff --git a/docs/figures/address_space.png b/docs/figures/address_space.png index 10744c5b2..205b936fc 100644 Binary files a/docs/figures/address_space.png and b/docs/figures/address_space.png differ diff --git a/docs/figures/neorv32_bus.png b/docs/figures/neorv32_bus.png index 806e8b660..d5e30cab2 100644 Binary files a/docs/figures/neorv32_bus.png and b/docs/figures/neorv32_bus.png differ diff --git a/rtl/core/neorv32_application_image.vhd b/rtl/core/neorv32_application_image.vhd index f92fd0ed9..a6b66a3f1 100644 --- a/rtl/core/neorv32_application_image.vhd +++ b/rtl/core/neorv32_application_image.vhd @@ -1,7 +1,7 @@ -- The NEORV32 RISC-V Processor - github.com/stnolting/neorv32 -- Auto-generated memory initialization image (for internal IMEM) -- Source: demo_blink_led/build/main.bin --- Built: 22.12.2024 15:13:19 +-- Built: 23.12.2024 21:23:52 library ieee; use ieee.std_logic_1164.all; @@ -11,8 +11,8 @@ use neorv32.neorv32_package.all; package neorv32_application_image is -constant application_init_size : natural := 1112; -- bytes -constant application_init_image : mem32_t := ( +constant application_init_size_c : natural := 1116; -- bytes +constant application_init_image_c : mem32_t := ( x"000020b7", x"80008093", x"30009073", @@ -46,7 +46,7 @@ x"00000e13", x"00000e93", x"00000f13", x"00000f93", -x"45800593", +x"45c00593", x"80000617", x"f7860613", x"80000697", @@ -67,9 +67,9 @@ x"00072023", x"00470713", x"ff5ff06f", x"00000417", -x"38440413", +x"38840413", x"00000497", -x"37c48493", +x"38048493", x"00945a63", x"00042083", x"000080e7", @@ -84,9 +84,9 @@ x"00000417", x"03840413", x"30541073", x"00000417", -x"34040413", +x"34440413", x"00000497", -x"33848493", +x"33c48493", x"00945a63", x"00042083", x"000080e7", @@ -115,12 +115,12 @@ x"00000513", x"00000593", x"00112623", x"00812423", -x"11c000ef", +x"120000ef", x"00000513", x"00150413", x"00000593", x"0ff57513", -x"108000ef", +x"10c000ef", x"0fa00513", x"020000ef", x"00040513", @@ -137,11 +137,11 @@ x"00912a23", x"00a12623", x"0f8000ef", x"3e800593", -x"1bc000ef", +x"1c0000ef", x"00c12603", x"00000693", x"00000593", -x"10c000ef", +x"110000ef", x"00050413", x"00058493", x"fc0027f3", @@ -164,7 +164,8 @@ x"01812403", x"01412483", x"02010113", x"00008067", -x"e0802783", +x"fffe07b7", +x"0087a783", x"00f79713", x"02075663", x"05c000ef", @@ -174,9 +175,9 @@ x"009585b3", x"00b504b3", x"048000ef", x"fe95eee3", -x"fcb492e3", +x"fcb490e3", x"fe856ae3", -x"fbdff06f", +x"fb9ff06f", x"01c49493", x"00445413", x"0084e433", @@ -185,19 +186,19 @@ x"00040863", x"fff40413", x"00000013", x"ff1ff06f", -x"f99ff06f", -x"c0000793", +x"f95ff06f", +x"fffc07b7", x"00a7a423", x"00b7a623", x"00008067", -x"fffff7b7", -x"40078793", +x"fff407b7", x"0047a583", x"0007a503", x"0047a703", x"fee59ae3", x"00008067", -x"e0002503", +x"fffe07b7", +x"0007a503", x"00008067", x"00050613", x"00000513", diff --git a/rtl/core/neorv32_boot_rom.vhd b/rtl/core/neorv32_boot_rom.vhd index 08e1d55cc..a44530d93 100644 --- a/rtl/core/neorv32_boot_rom.vhd +++ b/rtl/core/neorv32_boot_rom.vhd @@ -28,11 +28,11 @@ end neorv32_boot_rom; architecture neorv32_boot_rom_rtl of neorv32_boot_rom is -- determine physical ROM size in bytes (expand to next power of two) -- - constant boot_rom_size_index_c : natural := index_size_f((bootloader_init_image'length)); -- address with (32-bit entries) - constant boot_rom_size_c : natural range 0 to mem_boot_size_c := (2**boot_rom_size_index_c)*4; -- physical size in bytes + constant boot_rom_size_index_c : natural := index_size_f((bootloader_init_size_c)); -- address with (bytes) + constant boot_rom_size_c : natural range 0 to iodev_size_c := (2**boot_rom_size_index_c); -- physical size in bytes -- ROM initialized with executable code -- - constant mem_rom_c : mem32_t(0 to boot_rom_size_c/4-1) := mem32_init_f(bootloader_init_image, boot_rom_size_c/4); + constant mem_rom_c : mem32_t(0 to boot_rom_size_c/4-1) := mem32_init_f(bootloader_init_image_c, boot_rom_size_c/4); -- local signals -- signal rden : std_ulogic; diff --git a/rtl/core/neorv32_bootloader_image.vhd b/rtl/core/neorv32_bootloader_image.vhd index 3d6cdaf4a..e53757dfd 100644 --- a/rtl/core/neorv32_bootloader_image.vhd +++ b/rtl/core/neorv32_bootloader_image.vhd @@ -1,7 +1,7 @@ -- The NEORV32 RISC-V Processor - github.com/stnolting/neorv32 -- Auto-generated memory initialization image (for internal BOOTROM) -- Source: bootloader/build/main.bin --- Built: 22.12.2024 15:13:01 +-- Built: 23.12.2024 21:24:24 library ieee; use ieee.std_logic_1164.all; @@ -11,8 +11,8 @@ use neorv32.neorv32_package.all; package neorv32_bootloader_image is -constant bootloader_init_size : natural := 3916; -- bytes -constant bootloader_init_image : mem32_t := ( +constant bootloader_init_size_c : natural := 3960; -- bytes +constant bootloader_init_image_c : mem32_t := ( x"000020b7", x"80008093", x"30009073", @@ -20,10 +20,10 @@ x"00000097", x"0a408093", x"30509073", x"30401073", -x"80004217", +x"80200217", x"0e320213", x"ff027113", -x"80004197", +x"80200197", x"7d818193", x"00000293", x"00000313", @@ -31,10 +31,10 @@ x"00000393", x"00000413", x"00000493", x"00001597", -x"f0858593", -x"80004617", +x"f3458593", +x"80200617", x"fb460613", -x"80004697", +x"80200697", x"fac68693", x"00c58e63", x"00d65c63", @@ -43,7 +43,7 @@ x"00e62023", x"00458593", x"00460613", x"fedff06f", -x"80004717", +x"80200717", x"f8870713", x"80818793", x"00f75863", @@ -78,30 +78,32 @@ x"fec10113", x"0007a223", x"800007b7", x"0007a023", -x"ffffd7b7", +x"ffe017b7", x"00112823", x"00812623", x"00912423", -x"9bc78793", +x"9d878793", x"30579073", -x"e0802783", +x"fffe07b7", +x"0087a783", x"00d79713", -x"00075863", -x"80002023", -x"01100793", -x"80f02023", -x"e0802783", +x"00075a63", +x"fff807b7", +x"0007a023", +x"01100713", +x"00e7a023", +x"fffe07b7", +x"0087a783", x"2007f793", -x"06078463", -x"fffff7b7", -x"f007a023", -x"f007a423", +x"06078263", +x"ffef07b7", +x"0007a023", +x"0007a423", x"00006737", -x"f007a623", +x"0007a623", x"20570713", -x"f0e7a023", -x"f007a423", -x"f0078793", +x"00e7a023", +x"0007a423", x"0007a623", x"0007a703", x"00171693", @@ -118,23 +120,25 @@ x"000016b7", x"60068693", x"00d76733", x"00e7a023", -x"460000ef", -x"00050863", -x"00100793", -x"c0f02423", -x"c0002623", -x"fffff7b7", -x"5007a023", -x"e0002683", +x"46c000ef", +x"00050a63", +x"fffc07b7", +x"00100713", +x"00e7a423", +x"0007a623", +x"fff507b7", +x"0007a023", x"00009737", +x"fffe07b7", x"ffff7637", -x"00000793", +x"0007a683", x"5ff70713", +x"00000793", x"a0060613", -x"1ed76c63", +x"1ed76e63", x"00000713", x"3fe00613", -x"1ef66c63", +x"1ef66e63", x"fff78793", x"00679793", x"01079793", @@ -143,186 +147,186 @@ x"01877713", x"0107d793", x"00e7e7b3", x"0017e793", -x"fffff737", -x"50f72023", -x"e0802783", -x"00f79713", -x"02075863", -x"fffff7b7", -x"4007a023", -x"4007a223", -x"e0002703", +x"fff50737", +x"00f72023", +x"fffe0737", +x"00872783", +x"00f79693", +x"0206d863", +x"fff407b7", +x"0007a023", +x"0007a223", +x"00072703", x"00275713", -x"40e7a423", -x"4007a623", +x"00e7a423", +x"0007a623", x"08000793", x"30479073", x"00800793", x"3007a073", -x"ffffd537", -x"d1c50513", -x"6c4000ef", +x"ffe01537", +x"d4850513", +x"6c8000ef", x"f1302573", -x"658000ef", -x"ffffd537", -x"d5450513", -x"6b0000ef", -x"e0002503", +x"65c000ef", +x"ffe01537", +x"d8050513", +x"6b4000ef", +x"fffe0437", +x"00042503", x"644000ef", -x"ffffd537", -x"d5c50513", +x"ffe01537", +x"d8850513", x"69c000ef", x"30102573", x"630000ef", -x"ffffd537", -x"d6450513", +x"ffe01537", +x"d9050513", x"688000ef", x"fc002573", x"61c000ef", -x"ffffd537", -x"d6c50513", +x"ffe01537", +x"d9850513", x"674000ef", -x"e0802503", -x"00100413", -x"ffffd4b7", -x"600000ef", -x"ffffd537", -x"d7450513", -x"658000ef", -x"e0404503", -x"00a41533", +x"00842503", +x"00100493", +x"604000ef", +x"ffe01537", +x"da050513", +x"65c000ef", +x"00444503", +x"00a49533", x"ffc57513", -x"5e4000ef", -x"ffffd537", -x"d7c50513", -x"63c000ef", -x"e0504783", -x"00f41533", +x"5e8000ef", +x"ffe01537", +x"da850513", +x"640000ef", +x"00544783", +x"00f49533", x"ffc57513", -x"5c8000ef", -x"d1848513", +x"5cc000ef", +x"ffe014b7", +x"d4448513", x"624000ef", -x"e0802783", +x"00842783", x"00f79713", x"06075063", -x"ffffd537", -x"d8450513", +x"ffe01537", +x"db050513", x"60c000ef", x"308000ef", -x"e0002703", +x"00042703", x"00271413", x"00e40433", x"00141413", x"00a407b3", x"0087b433", x"00b40433", -x"e0802703", +x"fffe0737", +x"00872703", x"00e71693", -x"0c06d463", -x"fffff737", -x"50072683", -x"50070713", +x"0c06d063", +x"fff50737", +x"00072683", x"00f69613", -x"0a065a63", -x"ffffd537", +x"0a065863", +x"ffe01537", x"00472783", -x"db050513", +x"ddc50513", x"5bc000ef", -x"ffffd7b7", -x"dbc78513", +x"ffe017b7", +x"de878513", x"5b0000ef", -x"ffffd537", -x"e3c50513", +x"ffe01537", +x"e6850513", x"5a4000ef", -x"fffff7b7", -x"50078793", +x"fff507b7", x"0007a703", x"00f71693", x"fe06dce3", x"0047a403", x"0ff47413", x"00040513", -x"500000ef", -x"d1848513", -x"578000ef", +x"508000ef", +x"d4448513", +x"57c000ef", x"03f00793", x"24f40a63", x"f9b40413", x"0ff47413", x"01300793", x"2287e863", -x"ffffd7b7", -x"ed878793", +x"ffe017b7", +x"f0478793", x"00241413", x"00f40433", x"00042783", x"00078067", x"00c686b3", x"00178793", -x"e01ff06f", +x"dfdff06f", x"ffe70693", x"ffd6f693", x"00069863", x"0037d793", x"00170713", -x"df5ff06f", +x"df1ff06f", x"0017d793", x"ff5ff06f", x"00f12023", -x"214000ef", +x"218000ef", x"00012783", -x"f285e2e3", +x"f285e4e3", x"00b41463", -x"f0f56ee3", +x"f2f560e3", x"00100513", -x"6e4000ef", -x"d1848513", -x"4f4000ef", +x"6f8000ef", +x"d4448513", +x"4f8000ef", x"00000513", -x"019000ef", -x"ffffc2b7", +x"031000ef", +x"ffe002b7", x"00028067", x"00000513", -x"6c4000ef", -x"f2dff06f", +x"6d8000ef", +x"f31ff06f", x"800007b7", x"0047a403", x"00041863", -x"ffffd537", -x"e4450513", -x"f11ff06f", -x"ffffd537", -x"e6050513", -x"4b4000ef", +x"ffe01537", +x"e7050513", +x"f15ff06f", +x"ffe01537", +x"e8c50513", +x"4b8000ef", x"00040513", -x"448000ef", -x"ffffd537", -x"e6850513", -x"4a0000ef", +x"44c000ef", +x"ffe01537", +x"e9450513", +x"4a4000ef", x"00400537", -x"434000ef", -x"ffffd537", -x"e8050513", -x"48c000ef", -x"fffff7b7", -x"50078793", +x"438000ef", +x"ffe01537", +x"eac50513", +x"490000ef", +x"fff507b7", x"0007a703", x"00f71693", x"fe06dce3", x"0047a503", x"0ff57513", x"00a12023", -x"3e8000ef", +x"3f4000ef", x"00012503", x"07900793", -x"eaf518e3", -x"2f8000ef", +x"eaf51ce3", +x"304000ef", x"00050663", x"00300513", -x"49c000ef", -x"ffffd537", -x"e8c50513", -x"440000ef", +x"4a4000ef", +x"ffe01537", +x"eb850513", +x"448000ef", x"01045793", x"00178793", x"00400737", @@ -339,7 +343,7 @@ x"00b70733", x"00a78533", x"00e12223", x"00f12023", -x"2f0000ef", +x"2fc000ef", x"00012783", x"00412703", x"00478793", @@ -348,30 +352,30 @@ x"4788d5b7", x"afe58593", x"00400537", x"00e12023", -x"2cc000ef", +x"2d8000ef", x"00400537", x"00040593", x"00450513", -x"2bc000ef", +x"2c8000ef", x"00012703", x"00400537", x"00850513", x"40e005b3", -x"2a8000ef", -x"ffffd537", -x"d0050513", -x"df9ff06f", +x"2b4000ef", +x"ffe01537", +x"d2c50513", +x"e01ff06f", x"00f12223", -x"1ec000ef", -x"124000ef", +x"1f8000ef", +x"130000ef", x"0d800513", -x"0c8000ef", +x"0d0000ef", x"00012503", -x"0d8000ef", -x"0a4000ef", +x"0e4000ef", +x"0a8000ef", x"00412783", x"00f12223", -x"1e8000ef", +x"1f4000ef", x"00157513", x"00412783", x"fe0518e3", @@ -380,45 +384,48 @@ x"00010737", x"00e68733", x"f31ff06f", x"00100513", -x"e7dff06f", +x"e81ff06f", x"800007b7", x"0047a783", -x"e4079ee3", -x"ffffd537", -x"e9c50513", -x"d91ff06f", -x"e0802783", +x"e60790e3", +x"ffe01537", +x"ec850513", +x"d99ff06f", +x"fffe07b7", +x"0087a783", x"2007f793", x"00079863", -x"ffffd537", -x"eac50513", -x"d79ff06f", +x"ffe01537", +x"ed850513", +x"d7dff06f", x"00100513", x"e35ff06f", -x"ffffd537", -x"eb850513", -x"d65ff06f", -x"e0802503", +x"ffe01537", +x"ee450513", +x"d69ff06f", +x"fffe07b7", +x"0087a503", x"00f55513", x"00157513", x"00008067", -x"fffff7b7", -x"40078793", +x"fff407b7", x"0047a583", x"0007a503", x"0047a703", x"fee59ae3", x"00008067", -x"80002783", -x"00c79713", -x"fe074ce3", -x"800007b7", -x"80f02223", +x"fff807b7", +x"0007a703", +x"00c71693", +x"fe06cce3", +x"80000737", +x"00e7a223", x"00008067", -x"80a02223", -x"80002783", -x"fe07cee3", -x"80402503", +x"fff807b7", +x"00a7a223", +x"0007a703", +x"fe074ee3", +x"0047a503", x"0ff57513", x"00008067", x"ff810113", @@ -427,43 +434,43 @@ x"00050413", x"01055513", x"0ff57513", x"00112223", -x"fd1ff0ef", +x"fcdff0ef", x"00845513", x"0ff57513", -x"fc5ff0ef", +x"fc1ff0ef", x"0ff47513", x"00012403", x"00412083", x"00810113", -x"fb1ff06f", -x"80002783", -x"00c79713", -x"fe074ce3", +x"fadff06f", +x"fff80737", +x"00072783", +x"00c79693", +x"fe06cce3", x"800007b7", x"00878793", -x"80f02223", +x"00f72223", x"00008067", x"fe810113", x"00912623", x"00112a23", x"00812823", -x"00050713", +x"00050793", x"00000493", -x"04071a63", -x"fffff7b7", -x"50078793", -x"0007a683", +x"04079863", +x"fff50737", +x"00072683", x"00f69613", x"fe065ce3", -x"0047a403", +x"00472403", x"0ff47413", -x"00448793", +x"00448713", x"00810693", -x"00d787b3", -x"fe878e23", +x"00d70733", +x"fe870e23", x"00148493", -x"00400793", -x"fcf494e3", +x"00400713", +x"fce496e3", x"01412083", x"01012403", x"00812503", @@ -471,37 +478,37 @@ x"00c12483", x"01810113", x"00008067", x"00b48433", -x"00e12223", +x"00f12223", x"00b12023", x"f6dff0ef", x"00300513", -x"f11ff0ef", +x"f0dff0ef", x"00040513", x"f21ff0ef", x"00000513", -x"f01ff0ef", +x"efdff0ef", x"00050413", -x"ee1ff0ef", -x"00412703", +x"ed9ff0ef", +x"00412783", x"00012583", x"f95ff06f", x"ffc10113", x"00112023", x"f35ff0ef", x"00600513", -x"ed9ff0ef", +x"ed5ff0ef", x"00012083", x"00410113", -x"eb5ff06f", +x"eadff06f", x"ff810113", x"00112223", x"f15ff0ef", x"00500513", -x"eb9ff0ef", +x"eb5ff0ef", x"00000513", -x"eb1ff0ef", +x"eadff0ef", x"00a12023", -x"e91ff0ef", +x"e89ff0ef", x"00412083", x"00012503", x"00810113", @@ -510,8 +517,8 @@ x"ffc10113", x"00112023", x"ee1ff0ef", x"0ab00513", -x"e85ff0ef", -x"e69ff0ef", +x"e81ff0ef", +x"e61ff0ef", x"f95ff0ef", x"fb1ff0ef", x"00257793", @@ -519,8 +526,8 @@ x"fff00513", x"02078063", x"ebdff0ef", x"00400513", -x"e61ff0ef", -x"e45ff0ef", +x"e5dff0ef", +x"e3dff0ef", x"f91ff0ef", x"01e51513", x"41f55513", @@ -544,13 +551,13 @@ x"00f12023", x"f21ff0ef", x"e59ff0ef", x"00200513", -x"dfdff0ef", +x"df9ff0ef", x"00412703", x"00070513", x"e09ff0ef", x"00012503", -x"de9ff0ef", -x"dcdff0ef", +x"de5ff0ef", +x"dc5ff0ef", x"f19ff0ef", x"00157513", x"fe051ce3", @@ -562,8 +569,7 @@ x"01012403", x"00c12483", x"01810113", x"00008067", -x"fffff7b7", -x"50078793", +x"fff507b7", x"0007a703", x"00a71693", x"fe06cce3", @@ -575,18 +581,18 @@ x"00050413", x"03000513", x"00112423", x"00912023", -x"fcdff0ef", +x"fd1ff0ef", x"07800513", -x"fc5ff0ef", +x"fc9ff0ef", x"01c00493", x"00945733", -x"ffffd7b7", +x"ffe017b7", x"00f77713", -x"f2878793", +x"f5478793", x"00e787b3", x"0007c503", x"ffc48493", -x"fa1ff0ef", +x"fa5ff0ef", x"ffc00793", x"fcf49ee3", x"00812083", @@ -610,30 +616,31 @@ x"00008067", x"00a00793", x"00f49663", x"00d00513", -x"f41ff0ef", +x"f45ff0ef", x"00048513", -x"f39ff0ef", +x"f3dff0ef", x"fc9ff06f", x"ff810113", x"00812023", x"00050413", -x"ffffd537", -x"ca850513", +x"ffe01537", +x"cd450513", x"00112223", x"f99ff0ef", x"00241793", -x"ffffd537", +x"ffe01537", x"008787b3", -x"f3850513", +x"f6450513", x"00f50533", x"f81ff0ef", x"00800793", x"3007b073", -x"c65ff0ef", -x"00050863", -x"00100793", -x"c0f02423", -x"c0002623", +x"c61ff0ef", +x"00050a63", +x"fffc07b7", +x"00100713", +x"00e7a423", +x"0007a623", x"10500073", x"ffdff06f", x"fd010113", @@ -652,26 +659,28 @@ x"00f12023", x"342024f3", x"800007b7", x"00778793", -x"08f49463", -x"c05ff0ef", -x"00050863", -x"c0802783", +x"08f49863", +x"bfdff0ef", +x"00050a63", +x"fffc0737", +x"00872783", x"0017c793", -x"c0f02423", -x"e0802783", +x"00f72423", +x"fffe0437", +x"00842783", x"00f79713", x"02075863", -x"bf5ff0ef", -x"e0002783", -x"fffff737", +x"be9ff0ef", +x"00042783", +x"fff40737", x"fff00693", x"0027d793", x"00a78533", x"00f537b3", -x"40d72423", +x"00d72423", x"00b787b3", -x"40f72623", -x"40a72423", +x"00f72623", +x"00a72423", x"01c12403", x"02c12083", x"02812283", @@ -692,30 +701,31 @@ x"800007b7", x"0007a783", x"00078663", x"00100513", -x"ec9ff0ef", +x"ebdff0ef", x"34102473", -x"e0802783", +x"fffe07b7", +x"0087a783", x"00e79713", x"04075263", -x"ffffd537", -x"cb050513", -x"e5dff0ef", +x"ffe01537", +x"cdc50513", +x"e4dff0ef", x"00048513", -x"df1ff0ef", +x"de1ff0ef", x"02000513", -x"dcdff0ef", +x"dc1ff0ef", x"00040513", -x"de1ff0ef", +x"dd1ff0ef", x"02000513", -x"dbdff0ef", +x"db1ff0ef", x"34302573", -x"dd1ff0ef", -x"ffffd537", -x"d1850513", -x"e29ff0ef", +x"dc1ff0ef", +x"ffe01537", +x"d4450513", +x"e19ff0ef", x"00440413", x"34141073", -x"f55ff06f", +x"f51ff06f", x"fe010113", x"00912a23", x"00100793", @@ -725,42 +735,43 @@ x"00812c23", x"00a12023", x"00f4a023", x"02051863", -x"ffffd537", -x"cbc50513", -x"dedff0ef", +x"ffe01537", +x"ce850513", +x"dddff0ef", x"00012503", x"004005b7", -x"b85ff0ef", +x"b7dff0ef", x"4788d7b7", x"afe78793", -x"04f50663", +x"04f50863", x"00000513", -x"0340006f", -x"ffffd537", -x"cdc50513", -x"dc1ff0ef", +x"0380006f", +x"ffe01537", +x"d0850513", +x"db1ff0ef", x"00400537", -x"d55ff0ef", -x"ffffd537", -x"cf850513", -x"dadff0ef", -x"e0802783", +x"d45ff0ef", +x"ffe01537", +x"d2450513", +x"d9dff0ef", +x"fffe07b7", +x"0087a783", x"00d79713", x"00074663", x"00300513", -x"de9ff0ef", -x"c35ff0ef", -x"fa0504e3", +x"dd5ff0ef", +x"c25ff0ef", +x"fa0502e3", x"ff1ff06f", x"00012503", x"004005b7", x"00458593", -x"b21ff0ef", +x"b15ff0ef", x"00050413", x"00012503", x"004005b7", x"00858593", -x"b0dff0ef", +x"b01ff0ef", x"00050693", x"ffc47613", x"00000713", @@ -772,9 +783,9 @@ x"02c71e63", x"00d787b3", x"00200513", x"fa0792e3", -x"ffffd537", -x"d0050513", -x"d31ff0ef", +x"ffe01537", +x"d2c50513", +x"d1dff0ef", x"800007b7", x"0087a223", x"01c12083", @@ -788,7 +799,7 @@ x"00c12823", x"00e12623", x"00d12423", x"00f12223", -x"a9dff0ef", +x"a91ff0ef", x"00c12703", x"00412783", x"01012603", @@ -806,22 +817,22 @@ x"00a03533", x"40a00533", x"e0400437", x"00a47433", -x"ffffd537", -x"d0450513", -x"ca9ff0ef", -x"00040513", -x"c3dff0ef", -x"ffffd537", -x"d1450513", +x"ffe01537", +x"d3050513", x"c95ff0ef", -x"981ff0ef", -x"00050663", -x"c0002423", -x"c0002623", -x"fffff7b7", -x"50078793", -x"0007a703", -x"fe074ee3", +x"00040513", +x"c29ff0ef", +x"ffe01537", +x"d4050513", +x"c81ff0ef", +x"969ff0ef", +x"00050863", +x"fffc07b7", +x"0007a423", +x"0007a623", +x"fff50737", +x"00072783", +x"fe07cee3", x"000400e7", x"52450a07", x"00005f52", @@ -862,7 +873,7 @@ x"0a3e3e20", x"444c420a", x"44203a56", x"32206365", -x"30322032", +x"30322033", x"480a3432", x"203a5657", x"00000020", @@ -963,26 +974,26 @@ x"676e6974", x"6f656e2f", x"32337672", x"00000000", -x"ffffc5c0", -x"ffffc5e4", -x"ffffc5e4", -x"ffffc35c", -x"ffffc5e4", -x"ffffc5e4", -x"ffffc5e4", -x"ffffc5b8", -x"ffffc5e4", -x"ffffc5e4", -x"ffffc5e4", -x"ffffc5e4", -x"ffffc5e4", -x"ffffc42c", -x"ffffc440", -x"ffffc5e4", -x"ffffc434", -x"ffffc5e4", -x"ffffc5e4", -x"ffffc5d8", +x"ffe005d0", +x"ffe005f8", +x"ffe005f8", +x"ffe00374", +x"ffe005f8", +x"ffe005f8", +x"ffe005f8", +x"ffe005c8", +x"ffe005f8", +x"ffe005f8", +x"ffe005f8", +x"ffe005f8", +x"ffe005f8", +x"ffe00440", +x"ffe00454", +x"ffe005f8", +x"ffe00448", +x"ffe005f8", +x"ffe005f8", +x"ffe005e8", x"33323130", x"37363534", x"62613938", diff --git a/rtl/core/neorv32_bus.vhd b/rtl/core/neorv32_bus.vhd index 75a330824..7c681cd68 100644 --- a/rtl/core/neorv32_bus.vhd +++ b/rtl/core/neorv32_bus.vhd @@ -228,8 +228,8 @@ end neorv32_bus_reg_rtl; -- ================================================================================ -- -- NEORV32 SoC - Processor Bus Infrastructure: Section Gateway -- -- -------------------------------------------------------------------------------- -- --- Bus gateway to distribute accesses to 5 non-overlapping address sub-spaces -- --- (A to E). Note that the sub-spaces have to be aligned to their individual sizes. -- +-- Bus gateway to distribute accesses to 4 non-overlapping address sub-spaces -- +-- (A to D). Note that the sub-spaces have to be aligned to their individual sizes. -- -- All accesses that do not match any of these sections are redirected to the "X" -- -- port. The gateway-internal bus monitor ensures that all accesses are completed -- -- within a bound time window (if port's *_TMO_EN is true). Otherwise, a bus error -- @@ -257,35 +257,24 @@ entity neorv32_bus_gateway is A_BASE : std_ulogic_vector(31 downto 0); -- port address space base address A_SIZE : natural; -- port address space size in bytes (power of two), aligned to size A_TMO_EN : boolean; -- port access timeout enable - A_PRIV : boolean; -- privileged (M-mode) access only -- port B -- B_ENABLE : boolean; B_BASE : std_ulogic_vector(31 downto 0); B_SIZE : natural; B_TMO_EN : boolean; - B_PRIV : boolean; -- port C -- C_ENABLE : boolean; C_BASE : std_ulogic_vector(31 downto 0); C_SIZE : natural; C_TMO_EN : boolean; - C_PRIV : boolean; -- port D -- D_ENABLE : boolean; D_BASE : std_ulogic_vector(31 downto 0); D_SIZE : natural; D_TMO_EN : boolean; - D_PRIV : boolean; - -- port E -- - E_ENABLE : boolean; - E_BASE : std_ulogic_vector(31 downto 0); - E_SIZE : natural; - E_TMO_EN : boolean; - E_PRIV : boolean; -- port X (the void) -- X_ENABLE : boolean; - X_TMO_EN : boolean; - X_PRIV : boolean + X_TMO_EN : boolean ); port ( -- global control -- @@ -303,8 +292,6 @@ entity neorv32_bus_gateway is c_rsp_i : in bus_rsp_t; d_req_o : out bus_req_t; d_rsp_i : in bus_rsp_t; - e_req_o : out bus_req_t; - e_rsp_i : in bus_rsp_t; x_req_o : out bus_req_t; x_rsp_i : in bus_rsp_t ); @@ -313,22 +300,20 @@ end neorv32_bus_gateway; architecture neorv32_bus_gateway_rtl of neorv32_bus_gateway is -- port select -- - signal port_sel : std_ulogic_vector(5 downto 0); + signal port_sel : std_ulogic_vector(4 downto 0); - -- port enable and privileged access lists -- - type port_bool_list_t is array (0 to 5) of boolean; - constant port_en_list_c : port_bool_list_t := (A_ENABLE, B_ENABLE, C_ENABLE, D_ENABLE, E_ENABLE, X_ENABLE); - constant priv_acc_list_c : port_bool_list_t := (A_PRIV, B_PRIV, C_PRIV, D_PRIV, E_PRIV, X_PRIV); + -- port enable list -- + type port_bool_list_t is array (0 to 4) of boolean; + constant port_en_list_c : port_bool_list_t := (A_ENABLE, B_ENABLE, C_ENABLE, D_ENABLE, X_ENABLE); -- port timeout enable list -- - constant tmo_en_list_c : std_ulogic_vector(5 downto 0) := ( - bool_to_ulogic_f(X_TMO_EN), bool_to_ulogic_f(E_TMO_EN), bool_to_ulogic_f(D_TMO_EN), - bool_to_ulogic_f(C_TMO_EN), bool_to_ulogic_f(B_TMO_EN), bool_to_ulogic_f(A_TMO_EN) + constant tmo_en_list_c : std_ulogic_vector(4 downto 0) := ( + bool_to_ulogic_f(X_TMO_EN), bool_to_ulogic_f(D_TMO_EN), bool_to_ulogic_f(C_TMO_EN), bool_to_ulogic_f(B_TMO_EN), bool_to_ulogic_f(A_TMO_EN) ); -- gateway ports combined as arrays -- - type port_req_t is array (0 to 5) of bus_req_t; - type port_rsp_t is array (0 to 5) of bus_rsp_t; + type port_req_t is array (0 to 4) of bus_req_t; + type port_rsp_t is array (0 to 4) of bus_rsp_t; signal port_req : port_req_t; signal port_rsp : port_rsp_t; @@ -352,10 +337,9 @@ begin port_sel(1) <= '1' when B_ENABLE and (req_i.addr(31 downto index_size_f(B_SIZE)) = B_BASE(31 downto index_size_f(B_SIZE))) else '0'; port_sel(2) <= '1' when C_ENABLE and (req_i.addr(31 downto index_size_f(C_SIZE)) = C_BASE(31 downto index_size_f(C_SIZE))) else '0'; port_sel(3) <= '1' when D_ENABLE and (req_i.addr(31 downto index_size_f(D_SIZE)) = D_BASE(31 downto index_size_f(D_SIZE))) else '0'; - port_sel(4) <= '1' when E_ENABLE and (req_i.addr(31 downto index_size_f(E_SIZE)) = E_BASE(31 downto index_size_f(E_SIZE))) else '0'; -- accesses to the "void" are redirected to the X port -- - port_sel(5) <= '1' when X_ENABLE and (port_sel(4 downto 0) = "00000") else '0'; + port_sel(4) <= '1' when X_ENABLE and (port_sel(3 downto 0) = "0000") else '0'; -- Gateway Ports -------------------------------------------------------------------------- @@ -364,21 +348,16 @@ begin b_req_o <= port_req(1); port_rsp(1) <= b_rsp_i; c_req_o <= port_req(2); port_rsp(2) <= c_rsp_i; d_req_o <= port_req(3); port_rsp(3) <= d_rsp_i; - e_req_o <= port_req(4); port_rsp(4) <= e_rsp_i; - x_req_o <= port_req(5); port_rsp(5) <= x_rsp_i; + x_req_o <= port_req(4); port_rsp(4) <= x_rsp_i; -- bus request -- request: process(req_i, port_sel) begin - for i in 0 to 5 loop + for i in 0 to 4 loop port_req(i) <= req_terminate_c; if port_en_list_c(i) then -- port enabled port_req(i) <= req_i; - if priv_acc_list_c(i) then -- privileged-access only - port_req(i).stb <= port_sel(i) and req_i.stb and req_i.priv; - else - port_req(i).stb <= port_sel(i) and req_i.stb; - end if; + port_req(i).stb <= port_sel(i) and req_i.stb; end if; end loop; end process request; @@ -388,7 +367,7 @@ begin variable tmp_v : bus_rsp_t; begin tmp_v := rsp_terminate_c; -- start with all-zero - for i in 0 to 5 loop -- OR all response signals + for i in 0 to 4 loop -- OR all response signals if port_en_list_c(i) then -- port enabled tmp_v.data := tmp_v.data or port_rsp(i).data; tmp_v.ack := tmp_v.ack or port_rsp(i).ack; @@ -542,18 +521,18 @@ architecture neorv32_bus_io_switch_rtl of neorv32_bus_io_switch is -- bus register -- component neorv32_bus_reg generic ( - REQ_REG_EN : boolean := false; - RSP_REG_EN : boolean := false + REQ_REG_EN : boolean := false; + RSP_REG_EN : boolean := false ); port ( -- global control -- - clk_i : in std_ulogic; - rstn_i : in std_ulogic; + clk_i : in std_ulogic; + rstn_i : in std_ulogic; -- bus ports -- host_req_i : in bus_req_t; host_rsp_o : out bus_rsp_t; device_req_o : out bus_req_t; - device_rsp_i : in bus_rsp_t + device_rsp_i : in bus_rsp_t ); end component; diff --git a/rtl/core/neorv32_debug_dm.vhd b/rtl/core/neorv32_debug_dm.vhd index 90bb2d6d9..12278292c 100644 --- a/rtl/core/neorv32_debug_dm.vhd +++ b/rtl/core/neorv32_debug_dm.vhd @@ -19,7 +19,6 @@ use neorv32.neorv32_package.all; entity neorv32_debug_dm is generic ( - CPU_BASE_ADDR : std_ulogic_vector(31 downto 0); -- base address for the memory-mapped CPU interface registers AUTHENTICATOR : boolean -- implement authentication module when true ); port ( @@ -41,11 +40,11 @@ end neorv32_debug_dm; architecture neorv32_debug_dm_rtl of neorv32_debug_dm is - -- memory map -- - constant dm_code_base_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(CPU_BASE_ADDR) + x"00"); -- code ROM (park loop) - constant dm_pbuf_base_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(CPU_BASE_ADDR) + x"40"); -- program buffer (PBUF) - constant dm_data_base_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(CPU_BASE_ADDR) + x"80"); -- abstract data buffer (DATA) - constant dm_sreg_base_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(CPU_BASE_ADDR) + x"C0"); -- status register (SREG) + -- memory map; replicated throughout the entire device address space -- + constant dm_code_base_c : std_ulogic_vector(31 downto 0) := x"ffffff00"; -- code ROM (park loop) + constant dm_pbuf_base_c : std_ulogic_vector(31 downto 0) := x"ffffff40"; -- program buffer (PBUF) + constant dm_data_base_c : std_ulogic_vector(31 downto 0) := x"ffffff80"; -- abstract data buffer (DATA) + constant dm_sreg_base_c : std_ulogic_vector(31 downto 0) := x"ffffffC0"; -- status register (SREG) -- rv32i instruction prototypes -- constant instr_nop_c : std_ulogic_vector(31 downto 0) := x"00000013"; -- nop diff --git a/rtl/core/neorv32_imem.vhd b/rtl/core/neorv32_imem.vhd index a68c9b0d7..bdaaae97c 100644 --- a/rtl/core/neorv32_imem.vhd +++ b/rtl/core/neorv32_imem.vhd @@ -38,8 +38,7 @@ architecture neorv32_imem_rtl of neorv32_imem is constant alt_style_c : boolean := false; -- [TIP] enable this if synthesis fails to infer block RAM -- ROM - initialized with executable code -- - constant imem_app_size_c : natural := (application_init_image'length)*4; -- application (image) size in bytes - constant mem_rom_c : mem32_t(0 to IMEM_SIZE/4-1) := mem32_init_f(application_init_image, IMEM_SIZE/4); + constant mem_rom_c : mem32_t(0 to IMEM_SIZE/4-1) := mem32_init_f(application_init_image_c, IMEM_SIZE/4); -- local signals -- signal rdata : std_ulogic_vector(31 downto 0); @@ -60,8 +59,8 @@ begin "[NEORV32] Implementing processor-internal IMEM as " & cond_sel_string_f(IMEM_INIT, "pre-initialized ROM.", "blank RAM.") severity note; - assert not ((IMEM_INIT = true) and (imem_app_size_c > IMEM_SIZE)) report - "[NEORV32] Application image (" & natural'image(imem_app_size_c) & + assert not ((IMEM_INIT = true) and (application_init_size_c > IMEM_SIZE)) report + "[NEORV32] Application image (" & natural'image(application_init_size_c) & " bytes) does not fit into processor-internal IMEM (" & natural'image(IMEM_SIZE) & " bytes)!" severity error; diff --git a/rtl/core/neorv32_package.vhd b/rtl/core/neorv32_package.vhd index ef6bf09fa..36a4c4fe2 100644 --- a/rtl/core/neorv32_package.vhd +++ b/rtl/core/neorv32_package.vhd @@ -29,7 +29,7 @@ package neorv32_package is -- Architecture Constants ----------------------------------------------------------------- -- ------------------------------------------------------------------------------------------- - constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01100708"; -- hardware version + constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01100709"; -- hardware version constant archid_c : natural := 19; -- official RISC-V architecture ID constant XLEN : natural := 32; -- native data path width @@ -50,54 +50,52 @@ package neorv32_package is -- Main Address Regions (base address must be aligned to the region's size) --- constant mem_imem_base_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- IMEM size via generic constant mem_dmem_base_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- DMEM size via generic - constant mem_xip_base_c : std_ulogic_vector(31 downto 0) := x"e0000000"; -- page (4MSBs) only! + constant mem_xip_base_c : std_ulogic_vector(31 downto 0) := x"e0000000"; -- page (4 MSBs) only! constant mem_xip_size_c : natural := 256*1024*1024; - constant mem_boot_base_c : std_ulogic_vector(31 downto 0) := x"ffffc000"; - constant mem_boot_size_c : natural := 8*1024; - constant mem_io_base_c : std_ulogic_vector(31 downto 0) := x"ffffe000"; - constant mem_io_size_c : natural := 8*1024; -- = 32 * iodev_size_c + constant mem_io_base_c : std_ulogic_vector(31 downto 0) := x"ffe00000"; + constant mem_io_size_c : natural := 32*64*1024; -- = 32 * iodev_size_c - -- Start of uncached memory access (256MB page / 4MSBs only) -- + -- Start of uncached memory access (256MB page / 4 MSBs only) -- constant mem_uncached_begin_c : std_ulogic_vector(31 downto 0) := x"f0000000"; -- IO Address Map (base address must be aligned to the region's size) -- - constant iodev_size_c : natural := 256; -- size of a single IO device (bytes) ---constant base_io_???_c : std_ulogic_vector(31 downto 0) := x"ffffe000"; -- reserved ---constant base_io_???_c : std_ulogic_vector(31 downto 0) := x"ffffe100"; -- reserved ---constant base_io_???_c : std_ulogic_vector(31 downto 0) := x"ffffe200"; -- reserved ---constant base_io_???_c : std_ulogic_vector(31 downto 0) := x"ffffe300"; -- reserved ---constant base_io_???_c : std_ulogic_vector(31 downto 0) := x"ffffe400"; -- reserved ---constant base_io_???_c : std_ulogic_vector(31 downto 0) := x"ffffe500"; -- reserved ---constant base_io_???_c : std_ulogic_vector(31 downto 0) := x"ffffe600"; -- reserved ---constant base_io_???_c : std_ulogic_vector(31 downto 0) := x"ffffe700"; -- reserved ---constant base_io_???_c : std_ulogic_vector(31 downto 0) := x"ffffe800"; -- reserved ---constant base_io_???_c : std_ulogic_vector(31 downto 0) := x"ffffe900"; -- reserved - constant base_io_twd_c : std_ulogic_vector(31 downto 0) := x"ffffea00"; - constant base_io_cfs_c : std_ulogic_vector(31 downto 0) := x"ffffeb00"; - constant base_io_slink_c : std_ulogic_vector(31 downto 0) := x"ffffec00"; - constant base_io_dma_c : std_ulogic_vector(31 downto 0) := x"ffffed00"; - constant base_io_crc_c : std_ulogic_vector(31 downto 0) := x"ffffee00"; - constant base_io_xip_c : std_ulogic_vector(31 downto 0) := x"ffffef00"; - constant base_io_pwm_c : std_ulogic_vector(31 downto 0) := x"fffff000"; - constant base_io_gptmr_c : std_ulogic_vector(31 downto 0) := x"fffff100"; - constant base_io_onewire_c : std_ulogic_vector(31 downto 0) := x"fffff200"; - constant base_io_xirq_c : std_ulogic_vector(31 downto 0) := x"fffff300"; - constant base_io_mtime_c : std_ulogic_vector(31 downto 0) := x"fffff400"; - constant base_io_uart0_c : std_ulogic_vector(31 downto 0) := x"fffff500"; - constant base_io_uart1_c : std_ulogic_vector(31 downto 0) := x"fffff600"; - constant base_io_sdi_c : std_ulogic_vector(31 downto 0) := x"fffff700"; - constant base_io_spi_c : std_ulogic_vector(31 downto 0) := x"fffff800"; - constant base_io_twi_c : std_ulogic_vector(31 downto 0) := x"fffff900"; - constant base_io_trng_c : std_ulogic_vector(31 downto 0) := x"fffffa00"; - constant base_io_wdt_c : std_ulogic_vector(31 downto 0) := x"fffffb00"; - constant base_io_gpio_c : std_ulogic_vector(31 downto 0) := x"fffffc00"; - constant base_io_neoled_c : std_ulogic_vector(31 downto 0) := x"fffffd00"; - constant base_io_sysinfo_c : std_ulogic_vector(31 downto 0) := x"fffffe00"; - constant base_io_dm_c : std_ulogic_vector(31 downto 0) := x"ffffff00"; + constant iodev_size_c : natural := 64*1024; -- size of a single IO device (bytes) + constant base_io_bootrom_c : std_ulogic_vector(31 downto 0) := x"ffe00000"; +--constant base_io_???_c : std_ulogic_vector(31 downto 0) := x"ffe10000"; -- reserved +--constant base_io_???_c : std_ulogic_vector(31 downto 0) := x"ffe20000"; -- reserved +--constant base_io_???_c : std_ulogic_vector(31 downto 0) := x"ffe30000"; -- reserved +--constant base_io_???_c : std_ulogic_vector(31 downto 0) := x"ffe40000"; -- reserved +--constant base_io_???_c : std_ulogic_vector(31 downto 0) := x"ffe50000"; -- reserved +--constant base_io_???_c : std_ulogic_vector(31 downto 0) := x"ffe60000"; -- reserved +--constant base_io_???_c : std_ulogic_vector(31 downto 0) := x"ffe70000"; -- reserved +--constant base_io_???_c : std_ulogic_vector(31 downto 0) := x"ffe80000"; -- reserved +--constant base_io_???_c : std_ulogic_vector(31 downto 0) := x"ffe90000"; -- reserved + constant base_io_twd_c : std_ulogic_vector(31 downto 0) := x"ffea0000"; + constant base_io_cfs_c : std_ulogic_vector(31 downto 0) := x"ffeb0000"; + constant base_io_slink_c : std_ulogic_vector(31 downto 0) := x"ffec0000"; + constant base_io_dma_c : std_ulogic_vector(31 downto 0) := x"ffed0000"; + constant base_io_crc_c : std_ulogic_vector(31 downto 0) := x"ffee0000"; + constant base_io_xip_c : std_ulogic_vector(31 downto 0) := x"ffef0000"; + constant base_io_pwm_c : std_ulogic_vector(31 downto 0) := x"fff00000"; + constant base_io_gptmr_c : std_ulogic_vector(31 downto 0) := x"fff10000"; + constant base_io_onewire_c : std_ulogic_vector(31 downto 0) := x"fff20000"; + constant base_io_xirq_c : std_ulogic_vector(31 downto 0) := x"fff30000"; + constant base_io_mtime_c : std_ulogic_vector(31 downto 0) := x"fff40000"; + constant base_io_uart0_c : std_ulogic_vector(31 downto 0) := x"fff50000"; + constant base_io_uart1_c : std_ulogic_vector(31 downto 0) := x"fff60000"; + constant base_io_sdi_c : std_ulogic_vector(31 downto 0) := x"fff70000"; + constant base_io_spi_c : std_ulogic_vector(31 downto 0) := x"fff80000"; + constant base_io_twi_c : std_ulogic_vector(31 downto 0) := x"fff90000"; + constant base_io_trng_c : std_ulogic_vector(31 downto 0) := x"fffa0000"; + constant base_io_wdt_c : std_ulogic_vector(31 downto 0) := x"fffb0000"; + constant base_io_gpio_c : std_ulogic_vector(31 downto 0) := x"fffc0000"; + constant base_io_neoled_c : std_ulogic_vector(31 downto 0) := x"fffd0000"; + constant base_io_sysinfo_c : std_ulogic_vector(31 downto 0) := x"fffe0000"; + constant base_io_ocd_c : std_ulogic_vector(31 downto 0) := x"ffff0000"; -- On-Chip Debugger - Debug Module Entry Points (Code ROM) -- - constant dm_exc_entry_c : std_ulogic_vector(31 downto 0) := x"ffffff00"; -- = base_io_dm_c + 0, exceptions entry point - constant dm_park_entry_c : std_ulogic_vector(31 downto 0) := x"ffffff08"; -- = base_io_dm_c + 8, normal entry point + constant dm_exc_entry_c : std_ulogic_vector(31 downto 0) := x"ffffff00"; -- = base_io_ocd_c + code_rom + 0 + constant dm_park_entry_c : std_ulogic_vector(31 downto 0) := x"ffffff08"; -- = base_io_ocd_c + code_rom + 8 -- ********************************************************************************************************** -- SoC Definitions diff --git a/rtl/core/neorv32_top.vhd b/rtl/core/neorv32_top.vhd index 716ecd185..08c74e9c0 100644 --- a/rtl/core/neorv32_top.vhd +++ b/rtl/core/neorv32_top.vhd @@ -268,7 +268,7 @@ architecture neorv32_top_rtl of neorv32_top is constant bootrom_en_c : boolean := boolean(BOOT_MODE_SELECT = 0); constant imem_as_rom_c : boolean := boolean(BOOT_MODE_SELECT = 2); constant cpu_boot_addr_c : std_ulogic_vector(31 downto 0) := - cond_sel_suv_f(boolean(BOOT_MODE_SELECT = 0), mem_boot_base_c, + cond_sel_suv_f(boolean(BOOT_MODE_SELECT = 0), base_io_bootrom_c, cond_sel_suv_f(boolean(BOOT_MODE_SELECT = 1), BOOT_ADDR_CUSTOM, cond_sel_suv_f(boolean(BOOT_MODE_SELECT = 2), mem_imem_base_c, x"00000000"))); @@ -314,12 +314,12 @@ architecture neorv32_top_rtl of neorv32_top is signal cpu_i_rsp, cpu_d_rsp, icache_rsp, dcache_rsp, core_rsp, main_rsp, main2_rsp, dma_rsp : bus_rsp_t; -- bus: main sections -- - signal imem_req, dmem_req, xipcache_req, xip_req, boot_req, io_req, xcache_req, xbus_req : bus_req_t; - signal imem_rsp, dmem_rsp, xipcache_rsp, xip_rsp, boot_rsp, io_rsp, xcache_rsp, xbus_rsp : bus_rsp_t; + signal imem_req, dmem_req, xipcache_req, xip_req, io_req, xcache_req, xbus_req : bus_req_t; + signal imem_rsp, dmem_rsp, xipcache_rsp, xip_rsp, io_rsp, xcache_rsp, xbus_rsp : bus_rsp_t; -- bus: IO devices -- type io_devices_enum_t is ( - IODEV_OCD, IODEV_SYSINFO, IODEV_NEOLED, IODEV_GPIO, IODEV_WDT, IODEV_TRNG, IODEV_TWI, + IODEV_BOOTROM, IODEV_OCD, IODEV_SYSINFO, IODEV_NEOLED, IODEV_GPIO, IODEV_WDT, IODEV_TRNG, IODEV_TWI, IODEV_SPI, IODEV_SDI, IODEV_UART1, IODEV_UART0, IODEV_MTIME, IODEV_XIRQ, IODEV_ONEWIRE, IODEV_GPTMR, IODEV_PWM, IODEV_XIP, IODEV_CRC, IODEV_DMA, IODEV_SLINK, IODEV_CFS, IODEV_TWD ); @@ -719,35 +719,24 @@ begin A_BASE => mem_imem_base_c, A_SIZE => imem_size_c, A_TMO_EN => true, - A_PRIV => false, -- port B: internal DMEM -- B_ENABLE => MEM_INT_DMEM_EN, B_BASE => mem_dmem_base_c, B_SIZE => dmem_size_c, B_TMO_EN => true, - B_PRIV => false, -- port C: XIP -- C_ENABLE => XIP_EN, C_BASE => mem_xip_base_c, C_SIZE => mem_xip_size_c, C_TMO_EN => false, -- no timeout for XIP accesses - C_PRIV => false, - -- port D: BOOT ROM -- - D_ENABLE => bootrom_en_c, - D_BASE => mem_boot_base_c, - D_SIZE => mem_boot_size_c, + -- port D: IO -- + D_ENABLE => true, -- always enabled (but will be trimmed if no IO devices are implemented) + D_BASE => mem_io_base_c, + D_SIZE => mem_io_size_c, D_TMO_EN => true, - D_PRIV => true, -- only privileged (M-mode) accesses are allowed - -- port E: IO -- - E_ENABLE => true, -- always enabled (but will be trimmed if no IO devices are implemented) - E_BASE => mem_io_base_c, - E_SIZE => mem_io_size_c, - E_TMO_EN => true, - E_PRIV => true, -- only privileged (M-mode) accesses are allowed -- port X (the void): XBUS -- X_ENABLE => XBUS_EN, - X_TMO_EN => false, -- timeout handled by XBUS gateway - X_PRIV => false + X_TMO_EN => false -- timeout handled by XBUS gateway ) port map ( -- global control -- @@ -763,10 +752,8 @@ begin b_rsp_i => dmem_rsp, c_req_o => xip_req, c_rsp_i => xip_rsp, - d_req_o => boot_req, - d_rsp_i => boot_rsp, - e_req_o => io_req, - e_rsp_i => io_rsp, + d_req_o => io_req, + d_rsp_i => io_rsp, x_req_o => xbus_req, x_rsp_i => xbus_rsp ); @@ -823,25 +810,6 @@ begin end generate; - -- Processor-Internal Bootloader ROM (BOOTROM) -------------------------------------------- - -- ------------------------------------------------------------------------------------------- - neorv32_boot_rom_inst_true: - if bootrom_en_c generate - neorv32_boot_rom_inst: entity neorv32.neorv32_boot_rom - port map ( - clk_i => clk_i, - rstn_i => rstn_sys, - bus_req_i => boot_req, - bus_rsp_o => boot_rsp - ); - end generate; - - neorv32_boot_rom_inst_false: - if not bootrom_en_c generate - boot_rsp <= rsp_terminate_c; - end generate; - - -- Execute In-Place Module (XIP) ---------------------------------------------------------- -- ------------------------------------------------------------------------------------------- neorv32_xip_inst_true: @@ -991,81 +959,100 @@ begin neorv32_bus_io_switch_inst: entity neorv32.neorv32_bus_io_switch generic map ( INREG_EN => true, - OUTREG_EN => false, + OUTREG_EN => true, DEV_SIZE => iodev_size_c, -- size of a single IO device - DEV_00_EN => OCD_EN, DEV_00_BASE => base_io_dm_c, - DEV_01_EN => io_sysinfo_en_c, DEV_01_BASE => base_io_sysinfo_c, - DEV_02_EN => IO_NEOLED_EN, DEV_02_BASE => base_io_neoled_c, - DEV_03_EN => io_gpio_en_c, DEV_03_BASE => base_io_gpio_c, - DEV_04_EN => IO_WDT_EN, DEV_04_BASE => base_io_wdt_c, - DEV_05_EN => IO_TRNG_EN, DEV_05_BASE => base_io_trng_c, - DEV_06_EN => IO_TWI_EN, DEV_06_BASE => base_io_twi_c, - DEV_07_EN => IO_SPI_EN, DEV_07_BASE => base_io_spi_c, - DEV_08_EN => IO_SDI_EN, DEV_08_BASE => base_io_sdi_c, - DEV_09_EN => IO_UART1_EN, DEV_09_BASE => base_io_uart1_c, - DEV_10_EN => IO_UART0_EN, DEV_10_BASE => base_io_uart0_c, - DEV_11_EN => IO_MTIME_EN, DEV_11_BASE => base_io_mtime_c, - DEV_12_EN => io_xirq_en_c, DEV_12_BASE => base_io_xirq_c, - DEV_13_EN => IO_ONEWIRE_EN, DEV_13_BASE => base_io_onewire_c, - DEV_14_EN => IO_GPTMR_EN, DEV_14_BASE => base_io_gptmr_c, - DEV_15_EN => io_pwm_en_c, DEV_15_BASE => base_io_pwm_c, - DEV_16_EN => XIP_EN, DEV_16_BASE => base_io_xip_c, - DEV_17_EN => IO_CRC_EN, DEV_17_BASE => base_io_crc_c, - DEV_18_EN => IO_DMA_EN, DEV_18_BASE => base_io_dma_c, - DEV_19_EN => IO_SLINK_EN, DEV_19_BASE => base_io_slink_c, - DEV_20_EN => IO_CFS_EN, DEV_20_BASE => base_io_cfs_c, - DEV_21_EN => IO_TWD_EN, DEV_21_BASE => base_io_twd_c, - DEV_22_EN => false, DEV_22_BASE => (others => '0'), -- reserved - DEV_23_EN => false, DEV_23_BASE => (others => '0'), -- reserved - DEV_24_EN => false, DEV_24_BASE => (others => '0'), -- reserved - DEV_25_EN => false, DEV_25_BASE => (others => '0'), -- reserved - DEV_26_EN => false, DEV_26_BASE => (others => '0'), -- reserved - DEV_27_EN => false, DEV_27_BASE => (others => '0'), -- reserved - DEV_28_EN => false, DEV_28_BASE => (others => '0'), -- reserved - DEV_29_EN => false, DEV_29_BASE => (others => '0'), -- reserved - DEV_30_EN => false, DEV_30_BASE => (others => '0'), -- reserved - DEV_31_EN => false, DEV_31_BASE => (others => '0') -- reserved + DEV_00_EN => bootrom_en_c, DEV_00_BASE => base_io_bootrom_c, + DEV_01_EN => false, DEV_01_BASE => (others => '0'), -- reserved + DEV_02_EN => false, DEV_02_BASE => (others => '0'), -- reserved + DEV_03_EN => false, DEV_03_BASE => (others => '0'), -- reserved + DEV_04_EN => false, DEV_04_BASE => (others => '0'), -- reserved + DEV_05_EN => false, DEV_05_BASE => (others => '0'), -- reserved + DEV_06_EN => false, DEV_06_BASE => (others => '0'), -- reserved + DEV_07_EN => false, DEV_07_BASE => (others => '0'), -- reserved + DEV_08_EN => false, DEV_08_BASE => (others => '0'), -- reserved + DEV_09_EN => false, DEV_09_BASE => (others => '0'), -- reserved + DEV_10_EN => IO_TWD_EN, DEV_10_BASE => base_io_twd_c, + DEV_11_EN => IO_CFS_EN, DEV_11_BASE => base_io_cfs_c, + DEV_12_EN => IO_SLINK_EN, DEV_12_BASE => base_io_slink_c, + DEV_13_EN => IO_DMA_EN, DEV_13_BASE => base_io_dma_c, + DEV_14_EN => IO_CRC_EN, DEV_14_BASE => base_io_crc_c, + DEV_15_EN => XIP_EN, DEV_15_BASE => base_io_xip_c, + DEV_16_EN => io_pwm_en_c, DEV_16_BASE => base_io_pwm_c, + DEV_17_EN => IO_GPTMR_EN, DEV_17_BASE => base_io_gptmr_c, + DEV_18_EN => IO_ONEWIRE_EN, DEV_18_BASE => base_io_onewire_c, + DEV_19_EN => io_xirq_en_c, DEV_19_BASE => base_io_xirq_c, + DEV_20_EN => IO_MTIME_EN, DEV_20_BASE => base_io_mtime_c, + DEV_21_EN => IO_UART0_EN, DEV_21_BASE => base_io_uart0_c, + DEV_22_EN => IO_UART1_EN, DEV_22_BASE => base_io_uart1_c, + DEV_23_EN => IO_SDI_EN, DEV_23_BASE => base_io_sdi_c, + DEV_24_EN => IO_SPI_EN, DEV_24_BASE => base_io_spi_c, + DEV_25_EN => IO_TWI_EN, DEV_25_BASE => base_io_twi_c, + DEV_26_EN => IO_TRNG_EN, DEV_26_BASE => base_io_trng_c, + DEV_27_EN => IO_WDT_EN, DEV_27_BASE => base_io_wdt_c, + DEV_28_EN => io_gpio_en_c, DEV_28_BASE => base_io_gpio_c, + DEV_29_EN => IO_NEOLED_EN, DEV_29_BASE => base_io_neoled_c, + DEV_30_EN => io_sysinfo_en_c, DEV_30_BASE => base_io_sysinfo_c, + DEV_31_EN => OCD_EN, DEV_31_BASE => base_io_ocd_c ) port map ( clk_i => clk_i, rstn_i => rstn_sys, main_req_i => io_req, main_rsp_o => io_rsp, - dev_00_req_o => iodev_req(IODEV_OCD), dev_00_rsp_i => iodev_rsp(IODEV_OCD), - dev_01_req_o => iodev_req(IODEV_SYSINFO), dev_01_rsp_i => iodev_rsp(IODEV_SYSINFO), - dev_02_req_o => iodev_req(IODEV_NEOLED), dev_02_rsp_i => iodev_rsp(IODEV_NEOLED), - dev_03_req_o => iodev_req(IODEV_GPIO), dev_03_rsp_i => iodev_rsp(IODEV_GPIO), - dev_04_req_o => iodev_req(IODEV_WDT), dev_04_rsp_i => iodev_rsp(IODEV_WDT), - dev_05_req_o => iodev_req(IODEV_TRNG), dev_05_rsp_i => iodev_rsp(IODEV_TRNG), - dev_06_req_o => iodev_req(IODEV_TWI), dev_06_rsp_i => iodev_rsp(IODEV_TWI), - dev_07_req_o => iodev_req(IODEV_SPI), dev_07_rsp_i => iodev_rsp(IODEV_SPI), - dev_08_req_o => iodev_req(IODEV_SDI), dev_08_rsp_i => iodev_rsp(IODEV_SDI), - dev_09_req_o => iodev_req(IODEV_UART1), dev_09_rsp_i => iodev_rsp(IODEV_UART1), - dev_10_req_o => iodev_req(IODEV_UART0), dev_10_rsp_i => iodev_rsp(IODEV_UART0), - dev_11_req_o => iodev_req(IODEV_MTIME), dev_11_rsp_i => iodev_rsp(IODEV_MTIME), - dev_12_req_o => iodev_req(IODEV_XIRQ), dev_12_rsp_i => iodev_rsp(IODEV_XIRQ), - dev_13_req_o => iodev_req(IODEV_ONEWIRE), dev_13_rsp_i => iodev_rsp(IODEV_ONEWIRE), - dev_14_req_o => iodev_req(IODEV_GPTMR), dev_14_rsp_i => iodev_rsp(IODEV_GPTMR), - dev_15_req_o => iodev_req(IODEV_PWM), dev_15_rsp_i => iodev_rsp(IODEV_PWM), - dev_16_req_o => iodev_req(IODEV_XIP), dev_16_rsp_i => iodev_rsp(IODEV_XIP), - dev_17_req_o => iodev_req(IODEV_CRC), dev_17_rsp_i => iodev_rsp(IODEV_CRC), - dev_18_req_o => iodev_req(IODEV_DMA), dev_18_rsp_i => iodev_rsp(IODEV_DMA), - dev_19_req_o => iodev_req(IODEV_SLINK), dev_19_rsp_i => iodev_rsp(IODEV_SLINK), - dev_20_req_o => iodev_req(IODEV_CFS), dev_20_rsp_i => iodev_rsp(IODEV_CFS), - dev_21_req_o => iodev_req(IODEV_TWD), dev_21_rsp_i => iodev_rsp(IODEV_TWD), - dev_22_req_o => open, dev_22_rsp_i => rsp_terminate_c, -- reserved - dev_23_req_o => open, dev_23_rsp_i => rsp_terminate_c, -- reserved - dev_24_req_o => open, dev_24_rsp_i => rsp_terminate_c, -- reserved - dev_25_req_o => open, dev_25_rsp_i => rsp_terminate_c, -- reserved - dev_26_req_o => open, dev_26_rsp_i => rsp_terminate_c, -- reserved - dev_27_req_o => open, dev_27_rsp_i => rsp_terminate_c, -- reserved - dev_28_req_o => open, dev_28_rsp_i => rsp_terminate_c, -- reserved - dev_29_req_o => open, dev_29_rsp_i => rsp_terminate_c, -- reserved - dev_30_req_o => open, dev_30_rsp_i => rsp_terminate_c, -- reserved - dev_31_req_o => open, dev_31_rsp_i => rsp_terminate_c -- reserved + dev_00_req_o => iodev_req(IODEV_BOOTROM), dev_00_rsp_i => iodev_rsp(IODEV_BOOTROM), + dev_01_req_o => open, dev_01_rsp_i => rsp_terminate_c, -- reserved + dev_02_req_o => open, dev_02_rsp_i => rsp_terminate_c, -- reserved + dev_03_req_o => open, dev_03_rsp_i => rsp_terminate_c, -- reserved + dev_04_req_o => open, dev_04_rsp_i => rsp_terminate_c, -- reserved + dev_05_req_o => open, dev_05_rsp_i => rsp_terminate_c, -- reserved + dev_06_req_o => open, dev_06_rsp_i => rsp_terminate_c, -- reserved + dev_07_req_o => open, dev_07_rsp_i => rsp_terminate_c, -- reserved + dev_08_req_o => open, dev_08_rsp_i => rsp_terminate_c, -- reserved + dev_09_req_o => open, dev_09_rsp_i => rsp_terminate_c, -- reserved + dev_10_req_o => iodev_req(IODEV_TWD), dev_10_rsp_i => iodev_rsp(IODEV_TWD), + dev_11_req_o => iodev_req(IODEV_CFS), dev_11_rsp_i => iodev_rsp(IODEV_CFS), + dev_12_req_o => iodev_req(IODEV_SLINK), dev_12_rsp_i => iodev_rsp(IODEV_SLINK), + dev_13_req_o => iodev_req(IODEV_DMA), dev_13_rsp_i => iodev_rsp(IODEV_DMA), + dev_14_req_o => iodev_req(IODEV_CRC), dev_14_rsp_i => iodev_rsp(IODEV_CRC), + dev_15_req_o => iodev_req(IODEV_XIP), dev_15_rsp_i => iodev_rsp(IODEV_XIP), + dev_16_req_o => iodev_req(IODEV_PWM), dev_16_rsp_i => iodev_rsp(IODEV_PWM), + dev_17_req_o => iodev_req(IODEV_GPTMR), dev_17_rsp_i => iodev_rsp(IODEV_GPTMR), + dev_18_req_o => iodev_req(IODEV_ONEWIRE), dev_18_rsp_i => iodev_rsp(IODEV_ONEWIRE), + dev_19_req_o => iodev_req(IODEV_XIRQ), dev_19_rsp_i => iodev_rsp(IODEV_XIRQ), + dev_20_req_o => iodev_req(IODEV_MTIME), dev_20_rsp_i => iodev_rsp(IODEV_MTIME), + dev_21_req_o => iodev_req(IODEV_UART0), dev_21_rsp_i => iodev_rsp(IODEV_UART0), + dev_22_req_o => iodev_req(IODEV_UART1), dev_22_rsp_i => iodev_rsp(IODEV_UART1), + dev_23_req_o => iodev_req(IODEV_SDI), dev_23_rsp_i => iodev_rsp(IODEV_SDI), + dev_24_req_o => iodev_req(IODEV_SPI), dev_24_rsp_i => iodev_rsp(IODEV_SPI), + dev_25_req_o => iodev_req(IODEV_TWI), dev_25_rsp_i => iodev_rsp(IODEV_TWI), + dev_26_req_o => iodev_req(IODEV_TRNG), dev_26_rsp_i => iodev_rsp(IODEV_TRNG), + dev_27_req_o => iodev_req(IODEV_WDT), dev_27_rsp_i => iodev_rsp(IODEV_WDT), + dev_28_req_o => iodev_req(IODEV_GPIO), dev_28_rsp_i => iodev_rsp(IODEV_GPIO), + dev_29_req_o => iodev_req(IODEV_NEOLED), dev_29_rsp_i => iodev_rsp(IODEV_NEOLED), + dev_30_req_o => iodev_req(IODEV_SYSINFO), dev_30_rsp_i => iodev_rsp(IODEV_SYSINFO), + dev_31_req_o => iodev_req(IODEV_OCD), dev_31_rsp_i => iodev_rsp(IODEV_OCD) ); + -- Processor-Internal Bootloader ROM (BOOTROM) -------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_boot_rom_inst_true: + if bootrom_en_c generate + neorv32_boot_rom_inst: entity neorv32.neorv32_boot_rom + port map ( + clk_i => clk_i, + rstn_i => rstn_sys, + bus_req_i => iodev_req(IODEV_BOOTROM), + bus_rsp_o => iodev_rsp(IODEV_BOOTROM) + ); + end generate; + + neorv32_boot_rom_inst_false: + if not bootrom_en_c generate + iodev_rsp(IODEV_BOOTROM) <= rsp_terminate_c; + end generate; + + -- Custom Functions Subsystem (CFS) ------------------------------------------------------- -- ------------------------------------------------------------------------------------------- neorv32_cfs_inst_true: @@ -1693,7 +1680,6 @@ begin -- ------------------------------------------------------------------------------------------- neorv32_debug_dm_inst: entity neorv32.neorv32_debug_dm generic map ( - CPU_BASE_ADDR => base_io_dm_c, AUTHENTICATOR => OCD_AUTHENTICATION ) port map ( diff --git a/rtl/file_list_soc.f b/rtl/file_list_soc.f index b0f1390b1..058201bfc 100644 --- a/rtl/file_list_soc.f +++ b/rtl/file_list_soc.f @@ -22,10 +22,10 @@ NEORV32_RTL_PATH_PLACEHOLDER/core/neorv32_application_image.vhd NEORV32_RTL_PATH_PLACEHOLDER/core/neorv32_imem.vhd NEORV32_RTL_PATH_PLACEHOLDER/core/neorv32_dmem.vhd -NEORV32_RTL_PATH_PLACEHOLDER/core/neorv32_bootloader_image.vhd -NEORV32_RTL_PATH_PLACEHOLDER/core/neorv32_boot_rom.vhd NEORV32_RTL_PATH_PLACEHOLDER/core/neorv32_xip.vhd NEORV32_RTL_PATH_PLACEHOLDER/core/neorv32_xbus.vhd +NEORV32_RTL_PATH_PLACEHOLDER/core/neorv32_bootloader_image.vhd +NEORV32_RTL_PATH_PLACEHOLDER/core/neorv32_boot_rom.vhd NEORV32_RTL_PATH_PLACEHOLDER/core/neorv32_cfs.vhd NEORV32_RTL_PATH_PLACEHOLDER/core/neorv32_sdi.vhd NEORV32_RTL_PATH_PLACEHOLDER/core/neorv32_gpio.vhd diff --git a/sw/bootloader/bootloader.c b/sw/bootloader/bootloader.c index 7dcde75eb..c06ecd5c0 100644 --- a/sw/bootloader/bootloader.c +++ b/sw/bootloader/bootloader.c @@ -361,7 +361,7 @@ int main(void) { PRINT_TEXT("\n"); if (c == 'r') { // restart bootloader - asm volatile ("li t0, %[input_i]; jr t0" : : [input_i] "i" (BOOTLOADER_BASE_ADDRESS)); // jump to beginning of boot ROM + asm volatile ("li t0, %[input_i]; jr t0" : : [input_i] "i" (NEORV32_BOOTROM_BASE)); // jump to beginning of boot ROM __builtin_unreachable(); } else if (c == 'h') { // help menu diff --git a/sw/bootloader/makefile b/sw/bootloader/makefile index 1470ebbea..17f656968 100644 --- a/sw/bootloader/makefile +++ b/sw/bootloader/makefile @@ -13,7 +13,7 @@ EFFORT = -Os # Enable link-time-optimization USER_FLAGS += \ -Wl,--defsym,__neorv32_rom_size=4k \ --Wl,--defsym,__neorv32_rom_base=0xFFFFC000 \ +-Wl,--defsym,__neorv32_rom_base=0xFFE00000 \ -Wl,--defsym,__neorv32_ram_size=256 \ -DMAKE_BOOTLOADER \ -flto diff --git a/sw/image_gen/image_gen.c b/sw/image_gen/image_gen.c index a55353ad7..2a2d22579 100644 --- a/sw/image_gen/image_gen.c +++ b/sw/image_gen/image_gen.c @@ -212,8 +212,8 @@ int main(int argc, char *argv[]) { "\n" "package neorv32_application_image is\n" "\n" - "constant application_init_size : natural := %lu; -- bytes\n" - "constant application_init_image : mem32_t := (\n", + "constant application_init_size_c : natural := %lu; -- bytes\n" + "constant application_init_image_c : mem32_t := (\n", argv[4], argv[2], compile_time, raw_exe_size); fputs(tmp_string, output); @@ -276,8 +276,8 @@ int main(int argc, char *argv[]) { "\n" "package neorv32_bootloader_image is\n" "\n" - "constant bootloader_init_size : natural := %lu; -- bytes\n" - "constant bootloader_init_image : mem32_t := (\n", + "constant bootloader_init_size_c : natural := %lu; -- bytes\n" + "constant bootloader_init_image_c : mem32_t := (\n", argv[4], argv[2], compile_time, raw_exe_size); fputs(tmp_string, output); diff --git a/sw/lib/include/neorv32.h b/sw/lib/include/neorv32.h index 007153ac7..740e2538e 100644 --- a/sw/lib/include/neorv32.h +++ b/sw/lib/include/neorv32.h @@ -32,11 +32,9 @@ extern "C" { **************************************************************************/ /**@{*/ /** XIP-mapped memory base address */ -#define XIP_MEM_BASE_ADDRESS (0xE0000000U) -/** bootloader memory base address */ -#define BOOTLOADER_BASE_ADDRESS (0xFFFFC000U) +#define XIP_MEM_BASE_ADDRESS (0xE0000000U) /** peripheral/IO devices memory base address */ -#define IO_BASE_ADDRESS (0xFFFFE000U) +#define IO_BASE_ADDRESS (0XFFE00000U) /**@}*/ @@ -44,38 +42,38 @@ extern "C" { * @name IO Address Space Map - Peripheral/IO Devices **************************************************************************/ /**@{*/ -//#define NEORV32_???_BASE (0xFFFFE000U) /**< reserved */ -//#define NEORV32_???_BASE (0xFFFFE100U) /**< reserved */ -//#define NEORV32_???_BASE (0xFFFFE200U) /**< reserved */ -//#define NEORV32_???_BASE (0xFFFFE300U) /**< reserved */ -//#define NEORV32_???_BASE (0xFFFFE400U) /**< reserved */ -//#define NEORV32_???_BASE (0xFFFFE500U) /**< reserved */ -//#define NEORV32_???_BASE (0xFFFFE600U) /**< reserved */ -//#define NEORV32_???_BASE (0xFFFFE700U) /**< reserved */ -//#define NEORV32_???_BASE (0xFFFFE800U) /**< reserved */ -//#define NEORV32_???_BASE (0xFFFFE900U) /**< reserved */ -#define NEORV32_TWD_BASE (0xFFFFEA00U) /**< Two-Wire Device (TWD) */ -#define NEORV32_CFS_BASE (0xFFFFEB00U) /**< Custom Functions Subsystem (CFS) */ -#define NEORV32_SLINK_BASE (0xFFFFEC00U) /**< Stream Link Interface (SLINK) */ -#define NEORV32_DMA_BASE (0xFFFFED00U) /**< Direct Memory Access Controller (DMA) */ -#define NEORV32_CRC_BASE (0xFFFFEE00U) /**< Cyclic Redundancy Check Unit (DMA) */ -#define NEORV32_XIP_BASE (0xFFFFEF00U) /**< Execute In Place Module (XIP) */ -#define NEORV32_PWM_BASE (0xFFFFF000U) /**< Pulse Width Modulation Controller (PWM) */ -#define NEORV32_GPTMR_BASE (0xFFFFF100U) /**< General Purpose Timer (GPTMR) */ -#define NEORV32_ONEWIRE_BASE (0xFFFFF200U) /**< 1-Wire Interface Controller (ONEWIRE) */ -#define NEORV32_XIRQ_BASE (0xFFFFF300U) /**< External Interrupt Controller (XIRQ) */ -#define NEORV32_MTIME_BASE (0xFFFFF400U) /**< Machine System Timer (MTIME) */ -#define NEORV32_UART0_BASE (0xFFFFF500U) /**< Primary Universal Asynchronous Receiver and Transmitter (UART0) */ -#define NEORV32_UART1_BASE (0xFFFFF600U) /**< Secondary Universal Asynchronous Receiver and Transmitter (UART1) */ -#define NEORV32_SDI_BASE (0xFFFFF700U) /**< Serial Data Interface (SDI) */ -#define NEORV32_SPI_BASE (0xFFFFF800U) /**< Serial Peripheral Interface Controller (SPI) */ -#define NEORV32_TWI_BASE (0xFFFFF900U) /**< Two-Wire Interface Controller (TWI) */ -#define NEORV32_TRNG_BASE (0xFFFFFA00U) /**< True Random Number Generator (TRNG) */ -#define NEORV32_WDT_BASE (0xFFFFFB00U) /**< Watchdog Timer (WDT) */ -#define NEORV32_GPIO_BASE (0xFFFFFC00U) /**< General Purpose Input/Output Port Controller (GPIO) */ -#define NEORV32_NEOLED_BASE (0xFFFFFD00U) /**< Smart LED Hardware Interface (NEOLED) */ -#define NEORV32_SYSINFO_BASE (0xFFFFFE00U) /**< System Information Memory (SYSINFO) */ -#define NEORV32_DM_BASE (0xFFFFFF00U) /**< On-Chip Debugger - Debug Module (OCD) */ +#define NEORV32_BOOTROM_BASE (0xFFE00000U) /**< Bootloader ROM (BOOTROM) */ +//#define NEORV32_???_BASE (0xFFE10000U) /**< reserved */ +//#define NEORV32_???_BASE (0xFFE20000U) /**< reserved */ +//#define NEORV32_???_BASE (0xFFE30000U) /**< reserved */ +//#define NEORV32_???_BASE (0xFFE40000U) /**< reserved */ +//#define NEORV32_???_BASE (0xFFE50000U) /**< reserved */ +//#define NEORV32_???_BASE (0xFFE60000U) /**< reserved */ +//#define NEORV32_???_BASE (0xFFE70000U) /**< reserved */ +//#define NEORV32_???_BASE (0xFFE80000U) /**< reserved */ +//#define NEORV32_???_BASE (0xFFE90000U) /**< reserved */ +#define NEORV32_TWD_BASE (0xFFEA0000U) /**< Two-Wire Device (TWD) */ +#define NEORV32_CFS_BASE (0xFFEB0000U) /**< Custom Functions Subsystem (CFS) */ +#define NEORV32_SLINK_BASE (0xFFEC0000U) /**< Stream Link Interface (SLINK) */ +#define NEORV32_DMA_BASE (0xFFED0000U) /**< Direct Memory Access Controller (DMA) */ +#define NEORV32_CRC_BASE (0xFFEE0000U) /**< Cyclic Redundancy Check Unit (DMA) */ +#define NEORV32_XIP_BASE (0xFFEF0000U) /**< Execute In Place Module (XIP) */ +#define NEORV32_PWM_BASE (0xFFF00000U) /**< Pulse Width Modulation Controller (PWM) */ +#define NEORV32_GPTMR_BASE (0xFFF10000U) /**< General Purpose Timer (GPTMR) */ +#define NEORV32_ONEWIRE_BASE (0xFFF20000U) /**< 1-Wire Interface Controller (ONEWIRE) */ +#define NEORV32_XIRQ_BASE (0xFFF30000U) /**< External Interrupt Controller (XIRQ) */ +#define NEORV32_MTIME_BASE (0xFFF40000U) /**< Machine System Timer (MTIME) */ +#define NEORV32_UART0_BASE (0xFFF50000U) /**< Primary Universal Asynchronous Receiver and Transmitter (UART0) */ +#define NEORV32_UART1_BASE (0xFFF60000U) /**< Secondary Universal Asynchronous Receiver and Transmitter (UART1) */ +#define NEORV32_SDI_BASE (0xFFF70000U) /**< Serial Data Interface (SDI) */ +#define NEORV32_SPI_BASE (0xFFF80000U) /**< Serial Peripheral Interface Controller (SPI) */ +#define NEORV32_TWI_BASE (0xFFF90000U) /**< Two-Wire Interface Controller (TWI) */ +#define NEORV32_TRNG_BASE (0xFFFA0000U) /**< True Random Number Generator (TRNG) */ +#define NEORV32_WDT_BASE (0xFFFB0000U) /**< Watchdog Timer (WDT) */ +#define NEORV32_GPIO_BASE (0xFFFC0000U) /**< General Purpose Input/Output Port Controller (GPIO) */ +#define NEORV32_NEOLED_BASE (0xFFFD0000U) /**< Smart LED Hardware Interface (NEOLED) */ +#define NEORV32_SYSINFO_BASE (0xFFFE0000U) /**< System Information Memory (SYSINFO) */ +#define NEORV32_DM_BASE (0xFFFF0000U) /**< On-Chip Debugger - Debug Module (OCD) */ /**@}*/ diff --git a/sw/lib/include/neorv32_cfs.h b/sw/lib/include/neorv32_cfs.h index f23e80d5c..496355d46 100644 --- a/sw/lib/include/neorv32_cfs.h +++ b/sw/lib/include/neorv32_cfs.h @@ -29,7 +29,7 @@ /**@{*/ /** CFS module prototype */ typedef volatile struct __attribute__((packed,aligned(4))) { - uint32_t REG[64]; /**< offset 4*0..4*63: CFS register 0..63, user-defined */ + uint32_t REG[(64*1024)/4]; /**< CFS registers, user-defined */ } neorv32_cfs_t; /** CFS module hardware access (#neorv32_cfs_t) */ diff --git a/sw/svd/neorv32.svd b/sw/svd/neorv32.svd index ccc53b1d2..b1a3309e9 100644 --- a/sw/svd/neorv32.svd +++ b/sw/svd/neorv32.svd @@ -39,13 +39,13 @@ CFS Custom functions subsystem - 0xFFFFEB00 + 0xFFEB0000 CFS_FIRQ1 0 - 0x100 + 0x10000 registers @@ -122,7 +122,7 @@ SDI Serial data interface controller - 0xFFFFF700 + 0xFFF70000 SDI_FIRQ11 @@ -230,7 +230,7 @@ SLINK Stream Link Interface - 0xFFFFEC00 + 0xFFEC0000 SLINK_RX_FIRQ14 SLINK_TX_FIRQ15 @@ -383,7 +383,7 @@ DMA Direct memory access controller - 0xFFFFED00 + 0xFFED0000 DMA_FIRQ10 @@ -499,7 +499,7 @@ CRC Cyclic redundancy check unit - 0xFFFFEE00 + 0xFFEE0000 0 @@ -536,7 +536,7 @@ PWM Pulse-width modulation controller - 0xFFFFF000 + 0xFFF00000 0 @@ -585,7 +585,7 @@ XIP Execute In Place Module - 0xFFFFEF00 + 0xFFEF0000 0 @@ -686,7 +686,7 @@ GPTMR General purpose timer - 0xFFFFF100 + 0xFFF10000 GPTMR_FIRQ12 @@ -749,7 +749,7 @@ ONEWIRE 1-Wire Interface Controller - 0xFFFFF200 + 0xFFF20000 ONEWIRE_FIRQ13 @@ -848,7 +848,7 @@ XIRQ External interrupts controller - 0xFFFFF300 + 0xFFF30000 XIRQ_FIRQ8 @@ -887,7 +887,7 @@ MTIME Machine timer - 0xFFFFF400 + 0xFFF40000 0 @@ -924,7 +924,7 @@ UART0 Primary universal asynchronous receiver and transmitter - 0xFFFFF500 + 0xFFF50000 UART0_RX_FIRQ2 UART0_TX_FIRQ3 @@ -1064,7 +1064,7 @@ UART1 Secondary universal asynchronous receiver and transmitter - 0xFFFFF600 + 0xFFF60000 UART1_RX_FIRQ4 UART1_TX_FIRQ5 @@ -1081,7 +1081,7 @@ SPI Serial peripheral interface controller - 0xFFFFF800 + 0xFFF80000 SPI_FIRQ6 @@ -1216,7 +1216,7 @@ TWI Two-wire interface controller - 0xFFFFF900 + 0xFFF90000 TWI_FIRQ7 @@ -1320,7 +1320,7 @@ TWD Two-wire device controller - 0xFFFFEA00 + 0xFFEA0000 TWD_FIRQ0 @@ -1446,7 +1446,7 @@ TRNG True random number generator - 0xFFFFFA00 + 0xFFFA0000 0 @@ -1511,7 +1511,7 @@ WDT Watchdog timer - 0xFFFFFB00 + 0xFFFB0000 0 @@ -1584,7 +1584,7 @@ GPIO General purpose input/output port - 0xFFFFFC00 + 0xFFFC0000 0 @@ -1623,7 +1623,7 @@ NEOLED Smart LED hardware interface - 0xFFFFFD00 + 0xFFFD0000 NEOLED_FIRQ9 @@ -1724,7 +1724,7 @@ SYSINFO System configuration information memory - 0xFFFFFE00 + 0xFFFE0000 0