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Merge pull request #377 from stnolting/slink_irq_rework
⚠️ [rtl] rework SLINK module
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‎CHANGELOG.md

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@@ -32,6 +32,7 @@ mimpid = 0x01040312 => 01.04.03.12 => Version 01.04.03.12 => v1.4.3.12
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| Date (*dd.mm.yyyy*) | Version | Comment |
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|:-------------------:|:-------:|:--------|
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| 31.07.2022 | 1.7.4.7 | :warning: rework **SLINK** module; [#377](https://github.com/stnolting/neorv32/pull/377) |
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| 25.07.2022 | 1.7.4.6 | :warning: simplify memory configuration of **linker script**; :sparkles: add in-console configuration option; [#]375(https://github.com/stnolting/neorv32/pull/375) |
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| 22.07.2022 | 1.7.4.5 | add `CUSTOM_ID` generic; update bootloader; [#374](https://github.com/stnolting/neorv32/pull/374) |
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| 21.07.2022 | 1.7.4.4 | :lock: specify **physical memory attributes (PMA)** ;[#372](https://github.com/stnolting/neorv32/pull/372) |

‎docs/datasheet/soc_slink.adoc

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| | fast IRQ channel 11 | SLINK TX IRQ (see <<_processor_interrupts>>)
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|=======================
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**Overview**
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The SLINK component provides up to 8 independent RX (receiving) and TX (sending) links for moving
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stream data. The interface provides higher bandwidth and less latency than the external memory bus
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interface, which makes it ideally suited to couple custom stream processing units (like CORDICs, FFTs or
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cryptographic accelerators).
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interface, which makes it ideally suited to couple custom stream processing units.
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Each individual link provides an internal FIFO for data buffering. The FIFO depth is globally defined
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Each link provides an individual internal FIFO for data buffering. The FIFO depth is globally defined
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for all TX links via the _SLINK_TX_FIFO_ generic and for all RX links via the _SLINK_RX_FIFO_ generic.
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The FIFO depth has to be at least 1, which will implement a simple input/output register. The maximum
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value is limited to 32768 entries. Note that the FIFO depth has to be a power of two (for optimal
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logic mapping).
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value is limited to 32768 entries. Note that the FIFO depth has to be a power of two.
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The actual number of implemented RX/TX links is configured by the _SLINK_NUM_RX_ and _SLINK_NUM_TX_
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generics. The SLINK module will be synthesized only if at least one of these generics is greater than
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generics, respectively. The SLINK module will be synthesized only if at least one of these generics is greater than
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zero. All unimplemented links are internally terminated and their according output signals are set to zero.
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[NOTE]
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The NEORV32 stream link interfaces are compatible to the _AXI Stream_ specs.
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.Example Program
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[TIP]
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An example program for the SLINK module is available in `sw/example/demo_slink`.
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**Theory of Operation**
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The SLINK provides eight data registers (`DATA[i]`) to access the links (read accesses will access the RX links,
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write accesses will access the TX links), one control register (`CTRL`) and one status register (`STATUS`).
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The SLINK provides eight data registers (`DATA[i]`) to access the links (read accesses will access the RX link FIFOs,
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write accesses will access the TX link FIFOs), one control register (`CTRL`), one interrupt configuration register (`IRQ`)
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and two status registers - one for the RX links (`RX_STATUS`) and one for the TX links (`TX_STATUS`).
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The SLINK is globally activated by setting the control register's enable bit _SLINK_CTRL_EN_. Clearing this
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bit will reset all internal logic and will also clear all data FIFOs. The actual data links are accessed by
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reading or writing the according link data registers `DATA[0]` to `DATA[7]`. For example, writing the `DATA[0]`
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bit will reset all internal logic and will also clear all FIFOs. The actual data links are accessed by
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reading or writing the according link data registers `DATA[0]` to `DATA[7]`. For example, writing to `DATA[0]`
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will put the according data into the FIFO of TX link 0. Accordingly, reading from `DATA[0]` will return one data
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word from the FIFO of RX link 0.
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The current link status of each RX and TX channel is accessible via the `STATUS` register. Each link provides a
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read-only FIFO status flag in this register: the _SLINK_CTRL_RX_AVAIL_ flags indicate that there is _at least_
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one data word available in the according RX link's FIFO. The _SLINK_CTRL_TX_FREE_ flags indicate
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there is _at least_ one free entry in the according TX link's FIFO.
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The current link status of each RX and TX channel is accessible via the `*X_STATUS` registers. The FIFO's status
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signals that represent the fill level (empty, at least half full, full) are exposed as read-only flags via those two
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registers.
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[NOTE]
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Writing to a TX link's FIFO that is _full_ will have no effect. Reading data from a RX link's FIFO that is
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_empty_ will have no effect and will return the last valid data word.
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The "end of packet" signal `lst` is controlled by the status register's _SLINK_STATUS_RX_LAST_ and
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_SLINK_STATUS_TX_LAST_ bits. Note that the RX/TX `lst` signal is also buffered by the internal FIFOs.
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Setting a bit in _SLINK_STATUS_TX_LAST_ before writing data to `DATA` will set the `lst` signal when the
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written data word is actually send from the FIFO. Vice versa, a bit in _SLINK_STATUS_RX_LAST_ will be set
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if the according data word read from `DATA` was marked as "end of packet".
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The TX link's "end of packet" signal `slink_tx_lst_o` is controlled by the `TX_STATUS` register's _SLINK_TX_STATUS_LAST_
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bits. Note that these bits are also buffered by the internal TX FIFOs, so setting one of these bits before writing data to
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`DATA` will set the `slink_tx_lst_o` signal when the written data word is actually send from the FIFO. Vice versa, the
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_SLINK_RX_STATUS_LAST_ bits in `RX_STATUS` represent the level of the according `slink_rx_lst_i` input when a new data word
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was samples. These bits are also buffered in the internal RX FIFOs.
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**Data Transmission**
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To send (TX) data the program should ensure there is at least one left in the according link's FIFO by checking
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_SLINK_CTRL_TX_FREE_. To mark the current data word to-be-send as "end of packet" the according _SLINK_STATUS_TX_LAST_
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_SLINK_CTRL_TX_FREE_. To mark the current data word to-be-send as "end of packet" the according _SLINK_TX_STATUS_LAST_
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bit has to be set _before_ writing `DATA`.
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Receive (RX) is available when the according link's _SLINK_CTRL_RX_AVAIL_ bit is set. To check if the received data
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is marked as "end of packet" the according _SLINK_STATUS_RX_LAST_ has to be checked _before_ reading `DATA`.
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Received data (RX) is available when the according link's _SLINK_RX_STATUS_EMPTY_ bit is cleared. To check if the received
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data is marked as "end of packet" the according _SLINK_RX_STATUS_LAST_ bit has to be examined _before_ reading `DATA`.
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**Interface & Protocol**
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The SLINK interface consists of four signals `dat`, `val`, `rdy` and `lst` for each RX and TX link.
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Each signal is an "array" with eight entires (one for each link). Note that an entry in `slink_*x_dat` is 32-bit
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wide while entries in `slink_*x_val` and `slink_*x_rdy` are are just 1-bit wide.
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Each signal is constructed as an "array" with eight entries - one for each link. Note that an entry in `slink_*x_dat` is 32-bit
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wide while entries in `slink_*x_val`, `slink_*x_rdy` and `slink_*x_lst` are are just 1-bit wide.
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* `dat` contains the actual data word
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* `val` marks the current transmission cycle as valid
@@ -97,16 +102,27 @@ image::stream_link_interface.png[width=560,align=center]
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**SLINK Interrupts**
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The stream interface provides two independent CPU interrupts - one for RX conditions (data received) and one
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for TX conditions (ready to send). The RX interrupt is controlled per-link by the _SLINK_CTRL_RX_IRQ_EN_
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control register bits while the TX interrupt is controlled per-link by the _SLINK_CTRL_TX_IRQ_EN_ control
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register bits. If any enabled link fulfills the RX/TX interrupt condition a RX/TX interrupt request is
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sent to the CPU. Note that all RX and TX interrupt conditions are logically OR-ed.
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The stream interface provides two independent CPU interrupt channels - one for RX conditions and one
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for TX conditions. These IRQs can be used to signal specific FIFO conditions (e.g. "data available") to the
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CPU. The specific interrupt conditions are programmed per-link via the `IRQ` register.
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A 2-bit-coded value is used to enable the according link's interrupt and to specify the actual condition.
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[NOTE]
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Note that all enabled interrupt configurations are logically OR-ed for the CPU RX and TX interrupts, respectively.
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Hence, if **any** link fulfills the according interrupt configuration the according RX/TX interrupt request is
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sent to the CPU.
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For the TX links (in `IRQ` _SLINK_IRQ_TX_) the following interrupt conditions are supported:
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* `0-`: off, no interrupt from link
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* `10`: interrupt fires if FIFO _becomes_ not empty
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* `11`: interrupt fires if FIFO _becomes_ at least half full
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For the RX links (in `IRQ` _SLINK_IRQ_RX_) the following interrupt conditions are supported:
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* RX interrupt: if the FIFO of link _i_ changes from status "empty" to "not empty" (data available) and the
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according _SLINK_CTRL_RX_IRQ_EN_ bit is set the SLINK RX interrupt is triggered
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* TX interrupt: if the FIFO of link _i_ changes from status "full" to "not full" (ready to send) and the
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according _SLINK_CTRL_TX_IRQ_EN_ bit is set the SLINK TX interrupt is triggered
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* `0-`: off, no interrupt from link
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* `10`: interrupt fires if FIFO _becomes_ empty
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* `11`: interrupt fires if FIFO _becomes_ less than half full
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Once the SLINK's RX or TX CPU interrupt has become pending, it has to be explicitly cleared again by writing
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zero to the according <<_mip>> CSR bit(s).
@@ -119,18 +135,23 @@ zero to the according <<_mip>> CSR bit(s).
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[options="header",grid="all"]
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|=======================
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| Address | Name [C] | Bit(s) | R/W | Function
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.6+<| `0xfffffec0` .6+<| `NEORV32_SLINK.CTRL` <| `0` _SLINK_CTRL_EN_ ^| r/w | SLINK global enable
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<| `7:1` _reserved_ ^| r/- <| reserved, read as zero
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<| `11:8` _SLINK_CTRL_TX_FIFO_S3_ : _SLINK_CTRL_TX_FIFO_S0_ ^| r/- <| TX FIFO depth, log2(_SLINK_TX_FIFO_)
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<| `15:12` _SLINK_CTRL_RX_FIFO_S3_ : _SLINK_CTRL_RX_FIFO_S0_ ^| r/- <| RX FIFO depth, log2(_SLINK_RX_FIFO_)
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<| `23:13` _SLINK_CTRL_RX_IRQ_EN_MSB_ : _SLINK_CTRL_RX_IRQ_EN_LSB_ ^| r/- <| RX interrupt enable for link _i_
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<| `23:13` _SLINK_CTRL_TX_IRQ_EN_MSB_ : _SLINK_CTRL_TX_IRQ_EN_LSB_ ^| r/- <| TX interrupt enable for link _i_
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| `0xfffffec4` : `0xfffffecf` | - |`31:0` | r/- | _reserved_
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.4+<| `0xfffffed0` .4+<| `NEORV32_SLINK.STATUS` <|`7:0` _SLINK_STATUS_RX_AVAIL_MSB_ : _SLINK_STATUS_RX_AVAIL_LSB_ ^| r/- <| RX link _i_ FIFO is NOT empty (data available)
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<|`15:8` _SLINK_STATUS_TX_FREE_MSB_ : _SLINK_STATUS_TX_FREE_LSB_ ^| r/- <| TX link _i_ FIFO is NOT full (ready to send)
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<|`23:16` _SLINK_STATUS_RX_LAST_MSB_ : _SLINK_STATUS_RX_LAST_LSB_ ^| r/- <| Indicates end of packet for RX link _i_
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<|`31:24` _SLINK_STATUS_TX_LAST_MSB_ : _SLINK_STATUS_TX_LAST_LSB_ ^| r/w <| Set to indicate end of packet for TX link _i_
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| `0xfffffed4` : `0xfffffedf` | - |`31:0` | r/- | _reserved_
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.6+<| `0xfffffec0` .6+<| `NEORV32_SLINK.CTRL` <| `0` _SLINK_CTRL_EN_ ^| r/w | SLINK global enable/reset
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<| `7:1` _reserved_ ^| r/- <| _reserved_, returns zero
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<| `19:16` _SLINK_CTRL_RX_NUM_MSB_ : _SLINK_CTRL_RX_NUM_LSB_ ^| r/- <| Number of RX links (_SLINK_NUM_RX_)
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<| `23:20` _SLINK_CTRL_TX_NUM_MSB_ : _SLINK_CTRL_TX_NUM_LSB_ ^| r/- <| Number of TX links (_SLINK_NUM_TX_)
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<| `27:24` _SLINK_CTRL_RX_FIFO_MSB_ : _SLINK_CTRL_RX_FIFO_LSB_ ^| r/- <| RX FIFO depth, log2(_SLINK_RX_FIFO_)
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<| `31:28` _SLINK_CTRL_TX_FIFO_MSB_ : _SLINK_CTRL_TX_FIFO_MSB_ ^| r/- <| TX FIFO depth, log2(_SLINK_TX_FIFO_)
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.2+<| `0xfffffec4` .2+<| `NEORV32_SLINK.IRQ` <|`15:0` _SLINK_IRQ_RX_MSB_ : _SLINK_IRQ_RX_LSB_ ^| r/w <| RX link _i_ interrupt configuration (2 bits per link)
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<|`31:16` _SLINK_IRQ_TX_MSB_ : _SLINK_IRQ_TX_LSB_ ^| r/w <| TX link _i_ interrupt configuration (2 bits per link)
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.4+<| `0xfffffec8` .4+<| `NEORV32_SLINK.RX_STATUS` <|`7:0` _SLINK_RX_STATUS_EMPTY_MSB_ : _SLINK_RX_STATUS_EMPTY_LSB_ ^| r/- <| RX link _i_ FIFO empty
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<|`15:8` _SLINK_RX_STATUS_HALF_MSB_ : _SLINK_RX_STATUS_HALF_LSB_ ^| r/- <| RX link _i_ FIFO at least half full
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<|`23:16` _SLINK_RX_STATUS_FULL_MSB_ : _SLINK_RX_STATUS_FULL_LSB_ ^| r/- <| RX link _i_ FIFO full
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<|`31:24` _SLINK_RX_STATUS_LAST_MSB_ : _SLINK_RX_STATUS_LAST_LSB_ ^| r/- <| Current data word of RX link _i_ is marked as "end of packet"
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.4+<| `0xfffffecc` .4+<| `NEORV32_SLINK.TX_STATUS` <|`7:0` _SLINK_TX_STATUS_EMPTY_MSB_ : _SLINK_TX_STATUS_EMPTY_LSB_ ^| r/- <| TX link _i_ FIFO empty
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<|`15:8` _SLINK_TX_STATUS_HALF_MSB_ : _SLINK_TX_STATUS_HALF_LSB_ ^| r/- <| TX link _i_ FIFO at least half full
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<|`23:16` _SLINK_TX_STATUS_FULL_MSB_ : _SLINK_TX_STATUS_FULL_LSB_ ^| r/- <| TX link _i_ FIFO full
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<|`31:24` _SLINK_TX_STATUS_LAST_MSB_ : _SLINK_TX_STATUS_LAST_LSB_ ^| r/w <| Set to mark next data word of TX link _i_ is "end of packet"
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| `0xfffffed0` : `0xfffffedf` | - |`31:0` | r/- | _reserved_, returns zero
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| `0xfffffee0` | `NEORV32_SLINK.DATA[0]` | `31:0` | r/w | Link 0 RX/TX data
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| `0xfffffee4` | `NEORV32_SLINK.DATA[1]` | `31:0` | r/w | Link 1 RX/TX data
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| `0xfffffee8` | `NEORV32_SLINK.DATA[2]` | `31:0` | r/w | Link 2 RX/TX data

‎rtl/core/neorv32_package.vhd

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-- Architecture Constants (do not modify!) ------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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constant data_width_c : natural := 32; -- native data path width - do not change!
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constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01070406"; -- NEORV32 version - no touchy!
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constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01070407"; -- NEORV32 version - no touchy!
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constant archid_c : natural := 19; -- official RISC-V architecture ID - hands off!
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-- Check if we're inside the Matrix -------------------------------------------------------
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-- Stream Link Interface (SLINK) --
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constant slink_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffec0"; -- base address
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constant slink_size_c : natural := 16*4; -- module's address space size in bytes
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constant slink_ctrl_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffec0";
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constant slink_irq_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffec4";
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constant slink_rx_status_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffec8";
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constant slink_tx_status_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffecc";
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--constant slink_reserved_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffed0";
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--constant slink_reserved_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffed4";
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--constant slink_reserved_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffed8";
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--constant slink_reserved_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffedc";
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constant slink_link0_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffee0";
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constant slink_link1_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffee4";
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constant slink_link2_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffee8";
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constant slink_link3_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffeec";
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constant slink_link4_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffef0";
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constant slink_link5_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffef4";
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constant slink_link6_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffef7";
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constant slink_link7_c : std_ulogic_vector(data_width_c-1 downto 0) := x"fffffefc";
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-- reserved --
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--constant reserved_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff00"; -- base address

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