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✨ add time[h] CSRs (#556)
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‎CHANGELOG.md

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@@ -31,6 +31,7 @@ mimpid = 0x01040312 => Version 01.04.03.12 => v1.4.3.12
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| Date (*dd.mm.yyyy*) | Version | Comment |
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|:-------------------:|:-------:|:--------|
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| 17.03.2023 | 1.8.2.5 | add RISC-V `time[h]` CSRs (part of the `Zicntr` ISA extension); [#556](https://github.com/stnolting/neorv32/pull/556) |
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| 17.03.2023 | 1.8.2.4 | re-add VHDL process names; [#555](https://github.com/stnolting/neorv32/pull/555) |
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| 15.03.2023 | 1.8.2.3 | rtl reworks, cleanups and optimizations; [#550](https://github.com/stnolting/neorv32/pull/550) |
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| 11.03.2023 | 1.8.2.2 | :sparkles: add support for RISC-V `Zicond` ISA extension (conditional operations); [#546](https://github.com/stnolting/neorv32/pull/546) |

‎docs/datasheet/cpu.adoc

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@@ -459,10 +459,16 @@ code (see `sw/example/floating_point_test`).
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==== `Zicntr` ISA Extension
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The `Zicntr` ISA extension adds the basic cycle <<_cycleh>>, <<_mcycleh>> and instruction-retired
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<<_instreth>>, <<_minstreth>> counters. This extensions is stated as _mandatory_ by the RISC-V spec.
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However, area-constrained setups may remove support for these counters. Section <<_machine_counter_and_timer_csrs>>
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shows a list of all `Zicntr`-related CSRs.
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The `Zicntr` ISA extension adds the basic <<_cycleh>>, <<_mcycleh>>, <<_timeh>> and <<_instreth>>, <<_minstreth>>
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counter CSRs. Section <<_machine_counter_and_timer_csrs>> shows a list of all `Zicntr`-related CSRs.
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[NOTE]
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Note that the <<_timeh>> CSRs are implemented as just another user-level shadow copy of the machine-mode cycle
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counters <<_mcycleh>> (just like <<_cycleh>>).
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[NOTE]
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This extensions is stated as _mandatory_ by the RISC-V spec. However, area-constrained setups may remove
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support for these counters.
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==== `Zicond` ISA Extension

‎docs/datasheet/cpu_csr.adoc

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‎rtl/core/neorv32_cpu_control.vhd

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‎rtl/core/neorv32_package.vhd

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@@ -53,7 +53,7 @@ package neorv32_package is
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-- "response time window" for processor-internal modules --
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-- = cycles after which an *unacknowledged* internal bus access will timeout and trigger a bus fault exception
56-
constant max_proc_int_response_time_c : natural := 15; -- min 2
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constant max_proc_int_response_time_c : natural := 15; -- default = 15 (min 2)
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-- log2 of co-processor timeout cycles --
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constant cp_timeout_c : natural := 7; -- default = 7 (= 128 cycles)
@@ -65,7 +65,7 @@ package neorv32_package is
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6666
-- Architecture Constants (do not modify!) ------------------------------------------------
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-- -------------------------------------------------------------------------------------------
68-
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01080204"; -- hardware version
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constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01080205"; -- hardware version
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constant archid_c : natural := 19; -- official RISC-V architecture ID
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-- Check if we're inside the Matrix -------------------------------------------------------

‎sim/neorv32_tb.vhd

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@@ -180,7 +180,7 @@ begin
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if ci_mode then
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-- No need to send the full expectation in one big chunk
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check_uart(net, uart1_rx_handle, nul & nul);
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check_uart(net, uart1_rx_handle, "0/47" & cr & lf);
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check_uart(net, uart1_rx_handle, "0/46" & cr & lf);
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end if;
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-- Wait until all expected data has been received

‎sw/example/processor_check/main.c

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@@ -125,7 +125,7 @@ uint32_t pmp_num_regions;
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**************************************************************************/
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int main() {
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128-
uint32_t tmp_a, tmp_b;
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uint32_t tmp_a, tmp_b, tmp_c;
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uint8_t id;
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// disable machine-mode interrupts
@@ -313,58 +313,41 @@ int main() {
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// ----------------------------------------------------------
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// Test standard RISC-V performance counter [m]cycle[h]
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// Test standard RISC-V counters
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// ----------------------------------------------------------
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neorv32_cpu_csr_write(CSR_MCAUSE, mcause_never_c);
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PRINT_STANDARD("[%i] cycle counter ", cnt_test);
319+
PRINT_STANDARD("[%i] Zicntr counters ", cnt_test);
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cnt_test++;
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// make sure counter is enabled
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asm volatile ("csrci %[addr], %[imm]" : : [addr] "i" (CSR_MCOUNTINHIBIT), [imm] "i" (1<<CSR_MCOUNTINHIBIT_CY));
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// prepare overflow
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neorv32_cpu_set_mcycle(0x00000000FFFFFFFFULL);
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asm volatile ("nop"); // counter LOW should overflow here
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// get current cycle counter HIGH
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tmp_a = neorv32_cpu_csr_read(CSR_MCYCLEH);
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// make sure cycle counter high has incremented and there was no exception during access
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if ((tmp_a == 1) && (neorv32_cpu_csr_read(CSR_MCAUSE) == mcause_never_c)) {
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test_ok();
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}
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else {
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test_fail();
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}
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// ----------------------------------------------------------
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// Test standard RISC-V performance counter [m]instret[h]
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// ----------------------------------------------------------
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neorv32_cpu_csr_write(CSR_MCAUSE, mcause_never_c);
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PRINT_STANDARD("[%i] instret counter ", cnt_test);
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cnt_test++;
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if (neorv32_cpu_csr_read(CSR_MXISA) & (1 << CSR_MXISA_ZICNTR)) {
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cnt_test++;
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// make sure counter is enabled
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asm volatile ("csrci %[addr], %[imm]" : : [addr] "i" (CSR_MCOUNTINHIBIT), [imm] "i" (1<<CSR_MCOUNTINHIBIT_IR));
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// make sure counters are enabled
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neorv32_cpu_csr_clr(CSR_MCOUNTINHIBIT, (1<<CSR_MCOUNTINHIBIT_CY) | (1<<CSR_MCOUNTINHIBIT_IR));
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// prepare overflow
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neorv32_cpu_set_minstret(0x00000000FFFFFFFFULL);
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// prepare overflow
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neorv32_cpu_set_mcycle(0x00000000FFFFFFFFULL);
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neorv32_cpu_set_minstret(0x00000000FFFFFFFFULL);
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asm volatile ("nop"); // counter LOW should overflow here
331+
asm volatile ("nop");
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// get instruction counter HIGH
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tmp_a = neorv32_cpu_csr_read(CSR_INSTRETH);
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// get current counter HIGH words
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asm volatile ("rdcycleh %[rd]" : [rd] "=r" (tmp_a) : );
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asm volatile ("rdtimeh %[rd]" : [rd] "=r" (tmp_b) : );
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asm volatile ("rdinstreth %[rd]" : [rd] "=r" (tmp_c) : );
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362-
// make sure instruction counter high has incremented and there was no exception during access
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if ((tmp_a == 1) && (neorv32_cpu_csr_read(CSR_MCAUSE) == mcause_never_c)) {
364-
test_ok();
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// make sure cycle counter high has incremented and there was no exception during access
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if ((tmp_a == 1) && // cycle overflow
340+
(tmp_a == tmp_b) && // cycle = time
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(tmp_c == 1) && // instret overflow
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(neorv32_cpu_csr_read(CSR_MCAUSE) == mcause_never_c)) { // no exception
343+
test_ok();
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}
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else {
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test_fail();
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}
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}
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else {
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test_fail();
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PRINT_STANDARD("[skipped, n.a.]\n");
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}
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‎sw/lib/include/neorv32_cpu_csr.h

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@@ -146,9 +146,9 @@ enum NEORV32_CSR_enum {
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CSR_DSCRATCH0 = 0x7b2, /**< 0x7b2 - dscratch0 (-/-): Debug scratch register */
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/* machine counters and timers */
149-
CSR_MCYCLE = 0xb00, /**< 0xb00 - mcycle (r/w): Machine cycle counter low word */
150-
CSR_MINSTRET = 0xb02, /**< 0xb02 - minstret (r/w): Machine instructions-retired counter low word */
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149+
CSR_MCYCLE = 0xb00, /**< 0xb00 - mcycle (r/w): Machine cycle counter low word */
150+
//CSR_MTIME = 0xb01, /**< 0xb01 - mtime (r/w): MAchine time counter low word */
151+
CSR_MINSTRET = 0xb02, /**< 0xb02 - minstret (r/w): Machine instructions-retired counter low word */
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CSR_MHPMCOUNTER3 = 0xb03, /**< 0xb03 - mhpmcounter3 (r/w): Machine hardware performance monitor 3 counter low word */
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CSR_MHPMCOUNTER4 = 0xb04, /**< 0xb04 - mhpmcounter4 (r/w): Machine hardware performance monitor 4 counter low word */
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CSR_MHPMCOUNTER5 = 0xb05, /**< 0xb05 - mhpmcounter5 (r/w): Machine hardware performance monitor 5 counter low word */
@@ -179,9 +179,9 @@ enum NEORV32_CSR_enum {
179179
CSR_MHPMCOUNTER30 = 0xb1e, /**< 0xb1e - mhpmcounter30 (r/w): Machine hardware performance monitor 30 counter low word */
180180
CSR_MHPMCOUNTER31 = 0xb1f, /**< 0xb1f - mhpmcounter31 (r/w): Machine hardware performance monitor 31 counter low word */
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182-
CSR_MCYCLEH = 0xb80, /**< 0xb80 - mcycleh (r/w): Machine cycle counter high word */
183-
CSR_MINSTRETH = 0xb82, /**< 0xb82 - minstreth (r/w): Machine instructions-retired counter high word */
184-
182+
CSR_MCYCLEH = 0xb80, /**< 0xb80 - mcycleh (r/w): Machine cycle counter high word */
183+
//CSR_MTIMEH = 0xb81, /**< 0xb81 - mtimeh (r/w): Machine time counter high word */
184+
CSR_MINSTRETH = 0xb82, /**< 0xb82 - minstreth (r/w): Machine instructions-retired counter high word */
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CSR_MHPMCOUNTER3H = 0xb83, /**< 0xb83 - mhpmcounter3h (r/w): Machine hardware performance monitor 3 counter high word */
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CSR_MHPMCOUNTER4H = 0xb84, /**< 0xb84 - mhpmcounter4h (r/w): Machine hardware performance monitor 4 counter high word */
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CSR_MHPMCOUNTER5H = 0xb85, /**< 0xb85 - mhpmcounter5h (r/w): Machine hardware performance monitor 5 counter high word */
@@ -213,9 +213,9 @@ enum NEORV32_CSR_enum {
213213
CSR_MHPMCOUNTER31H = 0xb9f, /**< 0xb9f - mhpmcounter31h (r/w): Machine hardware performance monitor 31 counter high word */
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215215
/* user counters and timers */
216-
CSR_CYCLE = 0xc00, /**< 0xc00 - cycle (r/-): Cycle counter low word (from MCYCLE) */
217-
CSR_INSTRET = 0xc02, /**< 0xc02 - instret (r/-): Instructions-retired counter low word (from MINSTRET) */
218-
216+
CSR_CYCLE = 0xc00, /**< 0xc00 - cycle (r/-): Cycle counter low word (from MCYCLE) */
217+
CSR_TIME = 0xc01, /**< 0xc01 - time (r/-): Time counter low word */
218+
CSR_INSTRET = 0xc02, /**< 0xc02 - instret (r/-): Instructions-retired counter low word (from MINSTRET) */
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CSR_HPMCOUNTER3 = 0xc03, /**< 0xc03 - hpmcounter3 (r/-): User hardware performance monitor 3 counter low word */
220220
CSR_HPMCOUNTER4 = 0xc04, /**< 0xc04 - hpmcounter4 (r/-): User hardware performance monitor 4 counter low word */
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CSR_HPMCOUNTER5 = 0xc05, /**< 0xc05 - hpmcounter5 (r/-): User hardware performance monitor 5 counter low word */
@@ -246,9 +246,9 @@ enum NEORV32_CSR_enum {
246246
CSR_HPMCOUNTER30 = 0xc1e, /**< 0xc1e - hpmcounter30 (r/-): User hardware performance monitor 30 counter low word */
247247
CSR_HPMCOUNTER31 = 0xc1f, /**< 0xc1f - hpmcounter31 (r/-): User hardware performance monitor 31 counter low word */
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249-
CSR_CYCLEH = 0xc80, /**< 0xc80 - cycleh (r/-): Cycle counter high word (from MCYCLEH) */
250-
CSR_INSTRETH = 0xc82, /**< 0xc82 - instreth (r/-): Instructions-retired counter high word (from MINSTRETH) */
251-
249+
CSR_CYCLEH = 0xc80, /**< 0xc80 - cycleh (r/-): Cycle counter high word (from MCYCLEH) */
250+
CSR_TIMEH = 0xc81, /**< 0xc81 - timeh (r/-): Time counter high word */
251+
CSR_INSTRETH = 0xc82, /**< 0xc82 - instreth (r/-): Instructions-retired counter high word (from MINSTRETH) */
252252
CSR_HPMCOUNTER3H = 0xc83, /**< 0xc83 - hpmcounter3h (r/-): User hardware performance monitor 3 counter high word */
253253
CSR_HPMCOUNTER4H = 0xc84, /**< 0xc84 - hpmcounter4h (r/-): User hardware performance monitor 4 counter high word */
254254
CSR_HPMCOUNTER5H = 0xc85, /**< 0xc85 - hpmcounter5h (r/-): User hardware performance monitor 5 counter high word */

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