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Merge pull request #357 from stnolting/rtl_cleanup
[rtl] minor cleanups and typo fixes
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‎CHANGELOG.md

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@@ -32,6 +32,7 @@ mimpid = 0x01040312 => 01.04.03.12 => Version 01.04.03.12 => v1.4.3.12
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| Date (*dd.mm.yyyy*) | Version | Comment |
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|:----------:|:-------:|:--------|
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| 01.07.2022 | 1.7.3.3 | minor rtl cleanups; [#357](https://github.com/stnolting/neorv32/pull/357) |
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| 29.06.2022 | 1.7.3.2 | :test_tube: add experimental core complex wrapper for integration into the [**LiteX**](https://github.com/enjoy-digital/litex) SoC builder framework; [#353](https://github.com/stnolting/neorv32/pull/353) |
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| 28.06.2022 | 1.7.3.1 | :bug: fix bug that caused permanent CPU stall if illegal load/store instruction; [#356](https://github.com/stnolting/neorv32/pull/356) |
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| 23.06.2022 | [**:rocket:1.7.3**](https://github.com/stnolting/neorv32/releases/tag/v1.7.3) | **New release** _two years NEORV32!_ :tada: |

‎docs/datasheet/cpu_csr.adoc

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@@ -118,6 +118,10 @@ CSRs with the following notes ...
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| 0xfc0 | <<_mxisa>> | _CSR_MXISA_ | r/- | NEORV32-specific "extended" machine CPU ISA and extensions | `X`
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|=======================
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121+
.Debug-Mode CSRs
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[NOTE]
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The CSRs related to the CPU's debug mode (used by the on-chip debugger) are not listed here as they are not accessible by
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normal software. See sections <<_cpu_debug_mode_csrs>> and <<_trigger_module_csrs>> for more information about those CSRs.
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<<<
@@ -136,7 +140,7 @@ Otherwise any access to the floating-point CSRs will raise an illegal instructio
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[frame="topbot",grid="none"]
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|=======================
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| 0x001 | **Floating-point accrued exceptions** | `fflags`
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3+| Reset value: _UNDEFINED_
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3+| Reset value: _0x00000000_
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3+| The `fflags` CSR is compatible to the RISC-V specifications. It shows the accrued ("accumulated")
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exception flags in the lowest 5 bits. This CSR is only available if a floating-point CPU extension is enabled.
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See the RISC-V ISA spec for more information.
@@ -150,7 +154,7 @@ See the RISC-V ISA spec for more information.
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[frame="topbot",grid="none"]
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|=======================
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| 0x002 | **Floating-point dynamic rounding mode** | `frm`
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3+| Reset value: _UNDEFINED_
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3+| Reset value: _0x00000000_
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3+| The `frm` CSR is compatible to the RISC-V specifications and is used to configure the rounding modes using
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the lowest 3 bits. This CSR is only available if a floating-point CPU extension is enabled. See the RISC-V
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ISA spec for more information.
@@ -164,7 +168,7 @@ ISA spec for more information.
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[frame="topbot",grid="none"]
165169
|=======================
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| 0x003 | **Floating-point control and status register** | `fcsr`
167-
3+| Reset value: _UNDEFINED_
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3+| Reset value: _0x00000000_
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3+| The `fcsr` CSR is compatible to the RISC-V specifications. It provides combined read/write access to the
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`fflags` and `frm` CSRs. This CSR is only available if a floating-point CPU extension is enabled. See the
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RISC-V ISA spec for more information.
@@ -277,7 +281,7 @@ Machine-mode software can discover available `Z*` _sub-extensions_ (like `Zicsr`
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[frame="topbot",grid="none"]
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|=======================
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| 0x304 | **Machine interrupt-enable register** | `mie`
280-
3+| Reset value: _UNDEFINED_
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3+| Reset value: _0x00000000_
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3+| The `mie` CSR is compatible to the RISC-V specifications and features custom extensions for the fast
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interrupt channels. It is used to enabled specific interrupts sources. Please note that interrupts also have to be
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globally enabled via the `CSR_MSTATUS_MIE` flag of the `mstatus` CSR. The following bits are implemented
@@ -327,7 +331,7 @@ Hence, the trap handler's base address has to be aligned to a 4-byte boundary.
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[frame="topbot",grid="none"]
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|=======================
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| 0x306 | **Machine counter enable** | `mcounteren`
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3+| Reset value: _UNDEFINED_
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3+| Reset value: _0x00000000_
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3+| The `mcounteren` CSR is compatible to the RISC-V specifications. The bits of this CSR define which
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counter/timer CSR can be accessed (read) from code running in a less-privileged modes. For example,
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if user-level code tries to read from a counter/timer CSR without enabled access, an illegal instruction
@@ -714,7 +718,7 @@ information) or when the CPU is in sleep-mode.
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[frame="topbot",grid="none"]
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|=======================
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| 0x232 -0x33f | **Machine hardware performance monitor event selector** | `mhpmevent3` - `mhpmevent31`
717-
3+| Reset value: _UNDEFINED_
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3+| Reset value: _0x00000000_
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3+| The `mhpmevent*` CSRs are compatible to the RISC-V specifications. The value in these CSRs define
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the architectural events that cause an increment of the according `mhpmcounter*[h]` counter(s). All available events are
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listed in the table below. If more than one event is selected, the according counter will increment if _any_ of
@@ -780,7 +784,7 @@ bit of arbitrary event counters. The event(s) that trigger an increment of these
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[frame="topbot",grid="none"]
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|=======================
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| 0x320 | **Machine counter-inhibit register** | `mcountinhibit`
783-
3+| Reset value: _UNDEFINED_
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3+| Reset value: _0x00000000_
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3+| The `mcountinhibit` CSR is compatible to the RISC-V specifications. The bits in this register define which
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counter/timer CSR are allowed to perform an automatic increment. Automatic update is enabled if the
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according bit in `mcountinhibit` is cleared. The following bits are implemented (all remaining bits are

‎rtl/core/neorv32_cpu.vhd

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@@ -161,7 +161,7 @@ begin
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-- CPU ISA Configuration ---------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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assert false report
164-
"NEORV32 CPU ISA Configuration (MARCH): " &
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"NEORV32 CPU CONFIG NOTE: ISA (MARCH) = " &
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cond_sel_string_f(CPU_EXTENSION_RISCV_E, "RV32E", "RV32I") &
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cond_sel_string_f(CPU_EXTENSION_RISCV_M, "M", "") &
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cond_sel_string_f(CPU_EXTENSION_RISCV_C, "C", "") &
@@ -181,6 +181,9 @@ begin
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-- Sanity Checks --------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
184+
-- say hello --
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assert false report "The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32" severity note;
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-- simulation notifier --
185188
assert not (is_simulation_c = true) report "NEORV32 CPU WARNING! Assuming this is a simulation." severity warning;
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assert not (is_simulation_c = false) report "NEORV32 CPU NOTE: Assuming this is real hardware." severity note;
@@ -192,6 +195,7 @@ begin
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-- CPU boot address --
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assert not (CPU_BOOT_ADDR(1 downto 0) /= "00") report "NEORV32 CPU CONFIG ERROR! <CPU_BOOT_ADDR> has to be 32-bit aligned." severity error;
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assert false report "NEORV32 CPU CONFIG NOTE: Boot from address 0x" & to_hstring32_f(CPU_BOOT_ADDR) & "." severity note;
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196200
-- CSR system --
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assert not (CPU_EXTENSION_RISCV_Zicsr = false) report "NEORV32 CPU CONFIG WARNING! No exception/interrupt/trap/privileged features available when <CPU_EXTENSION_RISCV_Zicsr> = false." severity warning;
@@ -208,14 +212,14 @@ begin
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assert not (CPU_IPB_ENTRIES < 2) report "NEORV32 CPU CONFIG ERROR! Number of entries in instruction prefetch buffer <CPU_IPB_ENTRIES> has to be >= 2." severity error;
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210214
-- PMP --
211-
assert not (PMP_NUM_REGIONS > 0) report "NEORV32 CPU NOTE: Implementing " & positive'image(PMP_NUM_REGIONS) & " PMP regions." severity note;
215+
assert not (PMP_NUM_REGIONS > 0) report "NEORV32 CPU CONFIG NOTE: Implementing " & positive'image(PMP_NUM_REGIONS) & " PMP regions." severity note;
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assert not (PMP_NUM_REGIONS > 16) report "NEORV32 CPU CONFIG ERROR! Number of PMP regions <PMP_NUM_REGIONS> out of valid range (0..16)." severity error;
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assert not ((is_power_of_two_f(PMP_MIN_GRANULARITY) = false) and (PMP_NUM_REGIONS > 0)) report "NEORV32 CPU CONFIG ERROR! <PMP_MIN_GRANULARITY> has to be a power of two." severity error;
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assert not (PMP_MIN_GRANULARITY < 4) report "NEORV32 CPU CONFIG ERROR! <PMP_MIN_GRANULARITY> has to be >= 4 bytes." severity error;
215219
assert not ((CPU_EXTENSION_RISCV_Zicsr = false) and (PMP_NUM_REGIONS > 0)) report "NEORV32 CPU CONFIG ERROR! Physical memory protection (PMP) requires <CPU_EXTENSION_RISCV_Zicsr> extension to be enabled." severity error;
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217221
-- HPM counters --
218-
assert not ((CPU_EXTENSION_RISCV_Zihpm = true) and (HPM_NUM_CNTS > 0)) report "NEORV32 CPU NOTE: Implementing " & positive'image(HPM_NUM_CNTS) & " HPM counters." severity note;
222+
assert not ((CPU_EXTENSION_RISCV_Zihpm = true) and (HPM_NUM_CNTS > 0)) report "NEORV32 CPU CONFIG NOTE: Implementing " & positive'image(HPM_NUM_CNTS) & " HPM counters." severity note;
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assert not ((CPU_EXTENSION_RISCV_Zihpm = true) and (HPM_NUM_CNTS > 29)) report "NEORV32 CPU CONFIG ERROR! Number of HPM counters <HPM_NUM_CNTS> out of valid range (0..29)." severity error;
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assert not ((CPU_EXTENSION_RISCV_Zihpm = true) and ((HPM_CNT_WIDTH < 0) or (HPM_CNT_WIDTH > 64))) report "NEORV32 CPU CONFIG ERROR! HPM counter width <HPM_CNT_WIDTH> has to be 0..64 bit." severity error;
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assert not ((CPU_EXTENSION_RISCV_Zicsr = false) and (CPU_EXTENSION_RISCV_Zihpm = true)) report "NEORV32 CPU CONFIG ERROR! Hardware performance monitors extension <CPU_EXTENSION_RISCV_Zihpm> requires <CPU_EXTENSION_RISCV_Zicsr> extension to be enabled." severity error;
@@ -228,7 +232,7 @@ begin
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assert not ((CPU_EXTENSION_RISCV_DEBUG = true) and (CPU_EXTENSION_RISCV_Zifencei = false)) report "NEORV32 CPU CONFIG ERROR! Debug mode requires <CPU_EXTENSION_RISCV_Zifencei> extension to be enabled." severity error;
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230234
-- fast multiplication option --
231-
assert not (FAST_MUL_EN = true) report "NEORV32 CPU CONFIG NOTE: <FAST_MUL_EN> enabled. Trying to use DSP blocks for base ISA multiplications." severity note;
235+
assert not (FAST_MUL_EN = true) report "NEORV32 CPU CONFIG NOTE: <FAST_MUL_EN> enabled. Inferring DSP blocks for multiplications." severity note;
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-- fast shift option --
234238
assert not (FAST_SHIFT_EN = true) report "NEORV32 CPU CONFIG NOTE: <FAST_SHIFT_EN> enabled. Implementing full-parallel logic / barrel shifters." severity note;

‎rtl/core/neorv32_cpu_bus.vhd

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@@ -168,7 +168,7 @@ begin
168168
misaligned_d_check: process(rstn_i, clk_i)
169169
begin
170170
if (rstn_i = '0') then
171-
misaligned <= def_rst_val_c;
171+
misaligned <= '0';
172172
elsif rising_edge(clk_i) then
173173
if (ctrl_i(ctrl_bus_mo_we_c) = '1') then
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case data_size is -- data size
@@ -265,8 +265,8 @@ begin
265265
begin
266266
if (rstn_i = '0') then
267267
arbiter.pend <= '0';
268-
arbiter.rw <= def_rst_val_c;
269-
arbiter.err <= def_rst_val_c;
268+
arbiter.rw <= '0';
269+
arbiter.err <= '0';
270270
elsif rising_edge(clk_i) then
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if (arbiter.pend = '0') then -- idle
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arbiter.pend <= ctrl_i(ctrl_bus_wr_c) or ctrl_i(ctrl_bus_rd_c); -- start bus access

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