[docs] update TRNG sections

Author: stnolting

docs/datasheet/soc.adoc

@@ -435,8 +435,8 @@ table (the channel number also corresponds to the according FIRQ priority: 0 = h
 [options="header",grid="rows"]
 |=======================
 | Channel | Source | Description
-| 0       | - | _reserved_
-| 1       | <<_custom_functions_subsystem_cfs,CFS>> | custom functions subsystem (CFS) interrupt (user-defined)
+| 0       | <<_true_random_number_generator_trng,TRNG>> | TRNG data available interrupt
+| 1       | <<_custom_functions_subsystem_cfs,CFS>> | Custom functions subsystem (CFS) interrupt (user-defined)
 | 2       | <<_primary_universal_asynchronous_receiver_and_transmitter_uart0,UART0>> | UART0 RX FIFO level interrupt
 | 3       | <<_primary_universal_asynchronous_receiver_and_transmitter_uart0,UART0>> | UART0 TX FIFO level interrupt
 | 4       | <<_secondary_universal_asynchronous_receiver_and_transmitter_uart1,UART1>> | UART1 RX FIFO level interrupt

docs/datasheet/soc_trng.adoc

@@ -11,7 +11,7 @@
 | Top entity ports:       | none |
 | Configuration generics: | `IO_TRNG_EN`   | implement TRNG when `true`
 |                         | `IO_TRNG_FIFO` | data FIFO depth, min 1, has to be a power of two
-| CPU interrupts:         | - | none
+| CPU interrupts:         | fast IRQ channel 0 | TRNG data available interrupt (see <<_processor_interrupts>>)
 |=======================
 
 
@@ -53,18 +53,28 @@ of random data in a short time. The random data FIFO can be cleared at any time
 setting the `TRNG_CTRL_FIFO_CLR` flag. The FIFO depth can be retrieved by software via the `TRNG_CTRL_FIFO_*` bits.
 
 
+**TRNG Interrupt**
+
+As the neoTRNG is a rather slow entropy source, a "data available" interrupt is provided to inform the application
+software that new random data is available. This interrupt can be trigger by either of two conditions: trigger the
+interrupt if _any_ random data is available (i.e. the data FIFO is not empty; `TRNG_CTRL_IRQ_SEL = 0`) or trigger
+the interrupt if the random pool is full (i.e. the data FIFO is full; `TRNG_CTRL_IRQ_SEL = 1`).
+Once the TRNG interrupt has fired it remains pending until the actual cause of the interrupt is resolved.
+
+
 **Register Map**
 
 .TRNG register map (`struct NEORV32_TRNG`)
 [cols="<2,<1,<4,^1,<7"]
 [options="header",grid="all"]
 |=======================
 | Address | Name [C] | Bit(s), Name [C] | R/W | Function
-.8+<| `0xfffffa00` .8+<| `CTRL` <|`7:0`   `TRNG_CTRL_DATA_MSB : TRNG_CTRL_DATA_MSB` ^| r/- <| 8-bit random data
+.9+<| `0xfffffa00` .9+<| `CTRL` <|`7:0`   `TRNG_CTRL_DATA_MSB : TRNG_CTRL_DATA_MSB` ^| r/- <| 8-bit random data
                                 <|`15:8`   -                                        ^| r/- <| reserved, read as zero
                                 <|`19:16` `TRNG_CTRL_FIFO_MSB : TRNG_CTRL_FIFO_MSB` ^| r/- <| FIFO depth, log2(`IO_TRNG_FIFO`)
                                 <|`27:20`  -                                        ^| r/- <| reserved, read as zero
-                                <|`28`    `TRNG_CTRL_FIFO_CLR`                      ^| -/w <| flush random data FIFO when set; auto-clears
+                                <|`27`    `TRNG_CTRL_IRQ_SEL`                       ^| r/w <| interrupt trigger select (0 = data available, 1 = FIFO full)
+                                <|`28`    `TRNG_CTRL_FIFO_CLR`                      ^| -/w <| flush random data FIFO when set; flag auto-clears
                                 <|`29`    `TRNG_CTRL_SIM_MODE`                      ^| r/- <| simulation mode (PRNG!)
                                 <|`30`    `TRNG_CTRL_EN`                            ^| r/w <| TRNG enable
                                 <|`31`    `TRNG_CTRL_VALID`                         ^| r/- <| random data is valid when set