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🐛 Fix write access to mip.firq CSR bits (#821)
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‎CHANGELOG.md

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@@ -30,6 +30,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
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| Date | Version | Comment | Link |
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|:----:|:-------:|:--------|:----:|
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| 20.02.2024 | 1.9.5.6 | :bug: fix bug in `mip.firq` CSR access; `mip.firq` bits are now read-write - software can trigger FIRQs by writing `1` to the according CSR bit | [#821](https://github.com/stnolting/neorv32/pull/821) |
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| 19.02.2024 | 1.9.5.5 | SLINK: add native hardware support for AXI-stream's "tlast" signal | [#815](https://github.com/stnolting/neorv32/pull/815) |
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| 19.02.2024 | 1.9.5.4 | :warning: remove support of `Smcntrpmf` ISA extension (counter privilege mode filtering) | [#814](https://github.com/stnolting/neorv32/pull/814) |
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| 17.02.2024 | 1.9.5.3 | :warning: reworked CPU's hardware performance monitor (HPMs) events | [#811](https://github.com/stnolting/neorv32/pull/811) |

‎docs/datasheet/cpu_csr.adoc

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@@ -432,10 +432,7 @@ However, any write-access will be ignored and will not cause an exception to mai
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| Address | `0x344`
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| Reset value | `0x00000000`
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| ISA | `Zicsr`
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| Description | The `mip` CSR shows currently _pending_ machine-mode interrupt requests. The bits for the standard RISC-V
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machine-mode interrupts (`MEIP`, `MTIP`, `MSIP`) are read-only. Hence, these interrupts cannot be
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cleared/set using the `mip` register. These interrupts are cleared/acknowledged by mechanism that are
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specific for the interrupt-causing modules. the according interrupt-generating device.
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| Description | The `mip` CSR shows currently _pending_ machine-mode interrupt requests.
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|=======================
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.`mip` CSR bits
@@ -446,14 +443,17 @@ specific for the interrupt-causing modules. the according interrupt-generating d
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| 3 | `CSR_MIP_MSIP` | r/- | **MSIP**: Machine _software_ interrupt pending; _cleared by platform-defined mechanism_
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| 7 | `CSR_MIP_MTIP` | r/- | **MTIP**: Machine _timer_ interrupt pending; _cleared by platform-defined mechanism_
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| 11 | `CSR_MIP_MEIP` | r/- | **MEIP**: Machine _external_ interrupt pending; _cleared by platform-defined mechanism_
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| 31:16 | `CSR_MIP_FIRQ15P` : `CSR_MIP_FIRQ0P` | r/c | **FIRQxP**: Fast interrupt channel 15..0 pending; has to be cleared manually by writing zero
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| 31:16 | `CSR_MIP_FIRQ15P` : `CSR_MIP_FIRQ0P` | r/w | **FIRQxP**: Fast interrupt channel 15..0 pending; has to be cleared manually by writing zero
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|=======================
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.FIRQ Channel Mapping
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[TIP]
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See section <<_neorv32_specific_fast_interrupt_requests>> for the mapping of the FIRQ channels and the according
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interrupt-triggering processor module.
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[NOTE]
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The FIRQ channels can be triggered manually by software by writing `1` to the according `mip` bit.
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{empty} +
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[discrete]

‎rtl/core/neorv32_cpu_control.vhd

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Original file line numberDiff line numberDiff line change
@@ -255,7 +255,8 @@ architecture neorv32_cpu_control_rtl of neorv32_cpu_control is
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mie_mei : std_ulogic; -- machine external interrupt enable
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mie_mti : std_ulogic; -- machine timer interrupt enable
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mie_firq : std_ulogic_vector(15 downto 0); -- fast interrupt enable
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mip_firq_nclr : std_ulogic_vector(15 downto 0); -- clear pending FIRQ (active-low)
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mip_firq_wdata : std_ulogic_vector(15 downto 0); -- fast interrupt pending write data
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mip_firq_we : std_ulogic; -- fast interrupt pending write enable
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--
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privilege : std_ulogic; -- current privilege mode
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privilege_eff : std_ulogic; -- current *effective* privilege mode
@@ -1451,7 +1452,11 @@ begin
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-- NEORV32-specific fast interrupts --
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for i in 0 to 15 loop
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trap_ctrl.irq_pnd(irq_firq_0_c+i) <= (trap_ctrl.irq_pnd(irq_firq_0_c+i) and csr.mip_firq_nclr(i)) or firq_i(i);
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if (csr.mip_firq_we = '1') then -- write access to MIP(.FIRQ) CSR
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trap_ctrl.irq_pnd(irq_firq_0_c+i) <= firq_i(i) or csr.mip_firq_wdata(i); -- keep buffering incoming FIRQs
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else
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trap_ctrl.irq_pnd(irq_firq_0_c+i) <= firq_i(i) or trap_ctrl.irq_pnd(irq_firq_0_c+i); -- keep pending FIRQs alive
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end if;
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end loop;
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-- debug-mode entry --
@@ -1637,7 +1642,8 @@ begin
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csr.mtinst <= (others => '0');
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csr.mcounteren <= '0';
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csr.mcountinhibit <= (others => '0');
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csr.mip_firq_nclr <= (others => '0');
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csr.mip_firq_wdata <= (others => '0');
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csr.mip_firq_we <= '0';
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csr.dcsr_ebreakm <= '0';
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csr.dcsr_ebreaku <= '0';
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csr.dcsr_step <= '0';
@@ -1654,7 +1660,7 @@ begin
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-- defaults --
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csr.we <= csr.we_nxt and (not trap_ctrl.exc_buf(exc_illegal_c)); -- write if not an illegal instruction
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csr.mip_firq_nclr <= (others => '1'); -- inactive FIRQ clear (active low)
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csr.mip_firq_we <= '0'; -- no write to MIP.FIRQ by default
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csr.tdata1_hit_clr <= '0';
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-- ********************************************************************************
@@ -1715,7 +1721,8 @@ begin
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csr.mcause <= csr.wdata(31) & csr.wdata(4 downto 0); -- type (exception/interrupt) & identifier
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when csr_mip_c => -- machine interrupt pending
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csr.mip_firq_nclr <= csr.wdata(31 downto 16); -- set low to clear according bit (FIRQs only)
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csr.mip_firq_wdata <= csr.wdata(31 downto 16);
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csr.mip_firq_we <= '1'; -- trigger MIP.FIRQ write
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-- --------------------------------------------------------------------
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-- machine counter setup --

‎rtl/core/neorv32_package.vhd

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@@ -53,7 +53,7 @@ package neorv32_package is
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-- Architecture Constants -----------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01090505"; -- hardware version
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constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01090506"; -- hardware version
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constant archid_c : natural := 19; -- official RISC-V architecture ID
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constant XLEN : natural := 32; -- native data path width
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‎sw/lib/include/neorv32_cpu_csr.h

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@@ -304,22 +304,22 @@ enum NEORV32_CSR_MIP_enum {
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CSR_MIP_MEIP = 11, /**< CPU mip CSR (11): MEIP - Machine external interrupt pending (r/-) */
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/* NEORV32-specific extension: Fast Interrupt Requests (FIRQ) */
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CSR_MIP_FIRQ0P = 16, /**< CPU mip CSR (16): FIRQ0P - Fast interrupt channel 0 pending (r/c) */
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CSR_MIP_FIRQ1P = 17, /**< CPU mip CSR (17): FIRQ1P - Fast interrupt channel 1 pending (r/c) */
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CSR_MIP_FIRQ2P = 18, /**< CPU mip CSR (18): FIRQ2P - Fast interrupt channel 2 pending (r/c) */
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CSR_MIP_FIRQ3P = 19, /**< CPU mip CSR (19): FIRQ3P - Fast interrupt channel 3 pending (r/c) */
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CSR_MIP_FIRQ4P = 20, /**< CPU mip CSR (20): FIRQ4P - Fast interrupt channel 4 pending (r/c) */
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CSR_MIP_FIRQ5P = 21, /**< CPU mip CSR (21): FIRQ5P - Fast interrupt channel 5 pending (r/c) */
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CSR_MIP_FIRQ6P = 22, /**< CPU mip CSR (22): FIRQ6P - Fast interrupt channel 6 pending (r/c) */
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CSR_MIP_FIRQ7P = 23, /**< CPU mip CSR (23): FIRQ7P - Fast interrupt channel 7 pending (r/c) */
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CSR_MIP_FIRQ8P = 24, /**< CPU mip CSR (24): FIRQ8P - Fast interrupt channel 8 pending (r/c) */
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CSR_MIP_FIRQ9P = 25, /**< CPU mip CSR (25): FIRQ9P - Fast interrupt channel 9 pending (r/c) */
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CSR_MIP_FIRQ10P = 26, /**< CPU mip CSR (26): FIRQ10P - Fast interrupt channel 10 pending (r/c) */
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CSR_MIP_FIRQ11P = 27, /**< CPU mip CSR (27): FIRQ11P - Fast interrupt channel 11 pending (r/c) */
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CSR_MIP_FIRQ12P = 28, /**< CPU mip CSR (28): FIRQ12P - Fast interrupt channel 12 pending (r/c) */
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CSR_MIP_FIRQ13P = 29, /**< CPU mip CSR (29): FIRQ13P - Fast interrupt channel 13 pending (r/c) */
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CSR_MIP_FIRQ14P = 30, /**< CPU mip CSR (30): FIRQ14P - Fast interrupt channel 14 pending (r/c) */
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CSR_MIP_FIRQ15P = 31 /**< CPU mip CSR (31): FIRQ15P - Fast interrupt channel 15 pending (r/c) */
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CSR_MIP_FIRQ0P = 16, /**< CPU mip CSR (16): FIRQ0P - Fast interrupt channel 0 pending (r/w) */
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CSR_MIP_FIRQ1P = 17, /**< CPU mip CSR (17): FIRQ1P - Fast interrupt channel 1 pending (r/w) */
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CSR_MIP_FIRQ2P = 18, /**< CPU mip CSR (18): FIRQ2P - Fast interrupt channel 2 pending (r/w) */
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CSR_MIP_FIRQ3P = 19, /**< CPU mip CSR (19): FIRQ3P - Fast interrupt channel 3 pending (r/w) */
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CSR_MIP_FIRQ4P = 20, /**< CPU mip CSR (20): FIRQ4P - Fast interrupt channel 4 pending (r/w) */
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CSR_MIP_FIRQ5P = 21, /**< CPU mip CSR (21): FIRQ5P - Fast interrupt channel 5 pending (r/w) */
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CSR_MIP_FIRQ6P = 22, /**< CPU mip CSR (22): FIRQ6P - Fast interrupt channel 6 pending (r/w) */
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CSR_MIP_FIRQ7P = 23, /**< CPU mip CSR (23): FIRQ7P - Fast interrupt channel 7 pending (r/w) */
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CSR_MIP_FIRQ8P = 24, /**< CPU mip CSR (24): FIRQ8P - Fast interrupt channel 8 pending (r/w) */
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CSR_MIP_FIRQ9P = 25, /**< CPU mip CSR (25): FIRQ9P - Fast interrupt channel 9 pending (r/w) */
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CSR_MIP_FIRQ10P = 26, /**< CPU mip CSR (26): FIRQ10P - Fast interrupt channel 10 pending (r/w) */
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CSR_MIP_FIRQ11P = 27, /**< CPU mip CSR (27): FIRQ11P - Fast interrupt channel 11 pending (r/w) */
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CSR_MIP_FIRQ12P = 28, /**< CPU mip CSR (28): FIRQ12P - Fast interrupt channel 12 pending (r/w) */
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CSR_MIP_FIRQ13P = 29, /**< CPU mip CSR (29): FIRQ13P - Fast interrupt channel 13 pending (r/w) */
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CSR_MIP_FIRQ14P = 30, /**< CPU mip CSR (30): FIRQ14P - Fast interrupt channel 14 pending (r/w) */
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CSR_MIP_FIRQ15P = 31 /**< CPU mip CSR (31): FIRQ15P - Fast interrupt channel 15 pending (r/w) */
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};
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