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The NEORV32 Processor is a **customizable microcontroller-like system on chip (SoC)**written in platform-independent
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**VHDL** that is based on the NEORV32 [RISC-V](https://riscv.org/) CPU. The project is intended as auxiliary processor in larger SoC designs
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The NEORV32 Processor is a **customizable microcontroller-like system on chip (SoC)**built around the NEORV32
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[RISC-V](https://riscv.org/) CPU. The project is intended as auxiliary processor in larger SoC designs
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or as *ready-to-go* stand-alone custom microcontroller that even fits into a Lattice iCE40 UltraPlus 5k
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low-power & low-density FPGA running at 24+ MHz.
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@@ -35,6 +35,8 @@ are executed. Whenever an unexpected situation occurs the application code is in
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:interrobang: Want to know more? Check out the [project's rationale](https://stnolting.github.io/neorv32/#_rationale).
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:recycle: Looking for an **all-Verilog** version? Have a look at [neorv32-verilog](https://github.com/stnolting/neorv32-verilog).
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:books: For detailed information take a look at the [NEORV32 online documentation](https://stnolting.github.io/neorv32/).
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The latest _PDF_ versions can be found [here](https://github.com/stnolting/neorv32/releases/tag/nightly).
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@@ -51,20 +53,21 @@ various FPGA boards and toolchains to get you started. Also check out the list o
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[FreeRTOS](https://github.com/stnolting/neorv32/tree/main/sw/example/demo_freeRTOS) operating systems and
@@ -305,6 +312,7 @@ This overview provides some *quick links* to the most important sections of the
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*[Debugging via the On-Chip Debugger](https://stnolting.github.io/neorv32/ug/#_debugging_using_the_on_chip_debugger) - step through code *online* and *in-system*
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*[Simulation](https://stnolting.github.io/neorv32/ug/#_simulating_the_processor) - simulate the whole SoC
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*[LiteX Integration](https://stnolting.github.io/neorv32/ug/#_litex_soc_builder_support) - build a SoC using NEORV32 + [LiteX](https://github.com/enjoy-digital/litex)
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*[Convert to Verilog](https://stnolting.github.io/neorv32/ug/#_neorv32_in_verilog) - turn the NEORV32 into an all-Verilog design
* completely described in behavioral, platform-independent VHDL - no vendor- or technology-specific primitives, attributes, macros, libraries, etc. are used at all
If you are more of a Verilog fan or if your EDA toolchain does not support VHDL or mixed-language designs
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you can use an **all-Verilog** version of the processor provided by the https://github.com/stnolting/neorv32-verilog[`neorv32-verilog`] repository.
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[IMPORTANT]
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Note that this is **not a manual re-implementation of the core in Verilog** but rather an automated conversion.
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GHDL's synthesis feature is used to convert a pre-configured NEORV32 setup - including all peripherals, memories
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and memory images - into an unoptimized plain-Verilog netlist module file without any (technology-specific) primitives.
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.GHDL Synthesis
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[TIP]
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More information regarding GHDL's synthesis option can be found at https://ghdl.github.io/ghdl/using/Synthesis.html.
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An intermediate VHDL wrapper is provided that can be used to configure the processor (using VHDL generics) and to customize
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the interface ports. After conversion, a single Verilog file is generated that contains the whole NEORV32 processor.
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The original processor module hierarchy is preserved as well as most (all?) signal names, which allows easy inspection and debugging
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of simulation waveforms and synthesis results.
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.Example: interface of the resulting NEORV32 Verilog module (for a minimal SoC configuration)
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[source,verilog]
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----
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module neorv32_verilog_wrapper
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(input clk_i,
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input rstn_i,
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input uart0_rxd_i,
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output uart0_txd_o);
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----
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The generated Verilog netlist has been tested with
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