[sw/example] update example programs

Author: stnolting

sw/example/demo_dual_core/main.c

@@ -30,7 +30,7 @@ volatile uint8_t __attribute__ ((aligned (16))) core1_stack[2048]; // stack memo
  * Main function for core 0 (primary core).
  *
  * @attention This program requires the dual-core configuration, the CLINT, UART0
- * and the Zalrsc ISa extension.
+ * and the Zaamo ISA extension.
  *
  * @return Irrelevant (but can be inspected by the debugger).
  **************************************************************************/
@@ -57,8 +57,8 @@ int main(void) {
     neorv32_uart0_printf("[ERROR] CLINT module not available!\n");
     return -1;
   }
-  if ((neorv32_cpu_csr_read(CSR_MXISA) & (1<<CSR_MXISA_ZALRSC)) == 0) { // atomic lr/sc operations available?
-    neorv32_uart0_printf("[ERROR] 'Zalrsc' ISA extension not available!\n");
+  if ((neorv32_cpu_csr_read(CSR_MXISA) & (1<<CSR_MXISA_ZAAMO)) == 0) { // atomic memory operations available?
+    neorv32_uart0_printf("[ERROR] 'Zaamo' ISA extension not available!\n");
     return -1;
   }
 #ifndef __riscv_atomic

sw/example/demo_dual_core/run_check.sh

@@ -0,0 +1 @@
+make USER_FLAGS+="-DUART0_SIM_MODE -DUART1_SIM_MODE" clean_all asm install sim

sw/example/demo_dual_core/spinlock.c

@@ -1,6 +1,6 @@
 /**
  * @file spinlock.c
- * @brief Single simple spin-lock based on atomic lr/sc operations.
+ * @brief Single simple spin-lock based on atomic memory operations.
  */
 #include <neorv32.h>
 
@@ -18,7 +18,7 @@ static volatile uint32_t __spin_locked = 0;
  **************************************************************************/
 void spin_lock(void) {
 
-  while (neorv32_cpu_amoswapw((uint32_t)&__spin_locked, 1) != 0);
+  while(__sync_lock_test_and_set(&__spin_locked, -1)); // -> amoswap.w
 }
 
 
@@ -27,5 +27,6 @@ void spin_lock(void) {
  **************************************************************************/
 void spin_unlock(void) {
 
-  neorv32_cpu_amoswapw((uint32_t)&__spin_locked, 0);
+  //__sync_lock_release(&__spin_locked); // uses fence that is not required here
+  __sync_lock_test_and_set(&__spin_locked, 0); // -> amoswap.w
 }

sw/example/processor_check/main.c

@@ -85,7 +85,6 @@ volatile uint32_t constr_test = 0; // for constructor test
 
 volatile uint32_t dma_src; // dma source & destination data
 volatile uint32_t store_access_addr[2]; // variable to test store accesses
-volatile uint32_t amo_var; // variable for testing atomic memory accesses
 volatile uint32_t __attribute__((aligned(4))) pmp_access[2]; // variable to test pmp
 volatile uint32_t trap_cnt; // number of triggered traps
 volatile uint32_t pmp_num_regions; // number of implemented pmp regions
@@ -1976,88 +1975,6 @@ int main() {
   }
 
 
-  // ----------------------------------------------------------
-  // Test atomic lr/sc memory access - failing access
-  // ----------------------------------------------------------
-#if defined __riscv_atomic
-  neorv32_cpu_csr_write(CSR_MCAUSE, mcause_never_c);
-  PRINT_STANDARD("[%i] AMO LR/SC (", cnt_test);
-  PRINT_STANDARD("failing) ");
-
-  if (neorv32_cpu_csr_read(CSR_MXISA) & (1 << CSR_MXISA_ZALRSC)) {
-    cnt_test++;
-
-    // [NOTE] LR/SC operations bypass the data cache so we need to flush/reload
-    //        it before/after making "normal" load/store operations
-
-    amo_var = 0x00cafe00; // initialize
-    asm volatile ("fence"); // flush/reload d-cache
-
-    tmp_a = neorv32_cpu_amolr((uint32_t)&amo_var);
-    amo_var = 0x10cafe00; // break reservation
-    asm volatile ("fence"); // flush/reload d-cache
-    tmp_b = neorv32_cpu_amosc((uint32_t)&amo_var, 0xaaaaaaaa);
-    tmp_b = (tmp_b << 1) | neorv32_cpu_amosc((uint32_t)&amo_var, 0xcccccccc); // another SC: must fail
-    tmp_b = (tmp_b << 1) | neorv32_cpu_amosc((uint32_t)ADDR_UNREACHABLE, 0); // another SC: must fail; no bus exception!
-    asm volatile ("fence"); // flush/reload d-cache
-
-    if ((tmp_a   == 0x00cafe00) && // correct LR.W result
-        (amo_var == 0x10cafe00) && // atomic variable NOT updates by SC.W
-        (tmp_b   == 0x00000007) && // SC.W[2] failed, SC.W[1] failed, SC.W[0] failed
-        (neorv32_cpu_csr_read(CSR_MCAUSE) == mcause_never_c)) { // no exception
-      test_ok();
-    }
-    else {
-      test_fail();
-    }
-  }
-  else {
-    PRINT_STANDARD("[n.a.]\n");
-  }
-#endif
-
-
-  // ----------------------------------------------------------
-  // Test atomic lr/sc memory access - succeeding access
-  // ----------------------------------------------------------
-#if defined __riscv_atomic
-  neorv32_cpu_csr_write(CSR_MCAUSE, mcause_never_c);
-  PRINT_STANDARD("[%i] AMO LR/SC (", cnt_test);
-  PRINT_STANDARD("succeed) ");
-
-  if (neorv32_cpu_csr_read(CSR_MXISA) & (1 << CSR_MXISA_ZALRSC)) {
-    cnt_test++;
-
-    // [NOTE] LR/SC operations bypass the data cache so we need to flush/reload
-    //        it before/after making "normal" load/store operations
-
-    amo_var = 0x00abba00; // initialize
-    asm volatile ("fence"); // flush/reload d-cache
-
-    tmp_a = neorv32_cpu_amolr((uint32_t)&amo_var);
-    asm volatile ("fence"); // flush/reload d-cache
-    neorv32_cpu_load_unsigned_word((uint32_t)&amo_var); // dummy read, must not alter reservation set state
-    tmp_b = neorv32_cpu_amosc((uint32_t)&amo_var, 0xcccccccc);
-    tmp_b = (tmp_b << 1) | neorv32_cpu_amosc((uint32_t)&amo_var, 0xcccccccc); // another SC: must fail
-    tmp_b = (tmp_b << 1) | neorv32_cpu_amosc((uint32_t)ADDR_UNREACHABLE, 0); // another SC: must fail; no bus exception!
-    asm volatile ("fence"); // flush/reload d-cache
-
-    if ((tmp_a   == 0x00abba00) && // correct LR.W result
-        (amo_var == 0xcccccccc) && // atomic variable WAS updates by SC.W
-        (tmp_b   == 0x00000003) && // SC.W[2] succeeded, SC.W[1] failed, SC.W[0] failed
-        (neorv32_cpu_csr_read(CSR_MCAUSE) == mcause_never_c)) { // no exception
-      test_ok();
-    }
-    else {
-      test_fail();
-    }
-  }
-  else {
-    PRINT_STANDARD("[n.a.]\n");
-  }
-#endif
-
-
   // ----------------------------------------------------------
   // Test physical memory protection
   // ----------------------------------------------------------