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[control] minor edits
1 parent e80e134 commit 7a54bb6

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2 files changed

+5
-2
lines changed

2 files changed

+5
-2
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rtl/core/neorv32_cpu.vhd

+1
Original file line numberDiff line numberDiff line change
@@ -269,6 +269,7 @@ begin
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csr_rdata_o => csr_rdata, -- CSR read data
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-- external CSR interface --
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xcsr_we_o => xcsr_we, -- global write enable
272+
xcsr_re_o => open, -- global read enable
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xcsr_addr_o => xcsr_addr, -- address
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xcsr_wdata_o => xcsr_wdata, -- write data
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xcsr_rdata_i => xcsr_rdata_res, -- read data

rtl/core/neorv32_cpu_control.vhd

+4-2
Original file line numberDiff line numberDiff line change
@@ -96,6 +96,7 @@ entity neorv32_cpu_control is
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csr_rdata_o : out std_ulogic_vector(XLEN-1 downto 0); -- CSR read data
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-- external CSR interface --
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xcsr_we_o : out std_ulogic; -- global write enable
99+
xcsr_re_o : out std_ulogic; -- global read enable
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xcsr_addr_o : out std_ulogic_vector(11 downto 0); -- address
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xcsr_wdata_o : out std_ulogic_vector(XLEN-1 downto 0); -- write data
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xcsr_rdata_i : in std_ulogic_vector(XLEN-1 downto 0); -- read data
@@ -385,7 +386,7 @@ begin
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FIFO_WIDTH => ipb.wdata(i)'length, -- size of data elements in FIFO
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FIFO_RSYNC => false, -- we NEED to read data asynchronously
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FIFO_SAFE => false, -- no safe access required (ensured by FIFO-external logic)
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FULL_RESET => true -- map to FFs and add a dedicated reset
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FULL_RESET => false -- no need for a full hardware reset
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)
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port map (
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-- control --
@@ -1035,7 +1036,7 @@ begin
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end case;
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when opcode_amo_c => -- atomic memory operation
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if (exe_engine.ir(instr_funct3_msb_c downto instr_funct3_lsb_c) = "010") then
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if RISCV_ISA_Zaamo and (exe_engine.ir(instr_funct3_msb_c downto instr_funct3_lsb_c) = "010") then
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case exe_engine.ir(instr_funct5_msb_c downto instr_funct5_lsb_c) is
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when "00001" | "00000" | "00100" | "01100" | "01000" | "10000" | "10100" | "11000" | "11100" => illegal_cmd <= '0';
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when others => illegal_cmd <= '1';
@@ -1332,6 +1333,7 @@ begin
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-- External CSR Interface -----------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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xcsr_we_o <= csr.we;
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xcsr_re_o <= '1' when (exe_engine.state = EX_SYSTEM) else '0';
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xcsr_addr_o <= csr.addr;
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xcsr_wdata_o <= csr.wdata;
13371339

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