@@ -96,6 +96,7 @@ entity neorv32_cpu_control is
96
96
csr_rdata_o : out std_ulogic_vector (XLEN- 1 downto 0 ); -- CSR read data
97
97
-- external CSR interface --
98
98
xcsr_we_o : out std_ulogic ; -- global write enable
99
+ xcsr_re_o : out std_ulogic ; -- global read enable
99
100
xcsr_addr_o : out std_ulogic_vector (11 downto 0 ); -- address
100
101
xcsr_wdata_o : out std_ulogic_vector (XLEN- 1 downto 0 ); -- write data
101
102
xcsr_rdata_i : in std_ulogic_vector (XLEN- 1 downto 0 ); -- read data
@@ -385,7 +386,7 @@ begin
385
386
FIFO_WIDTH => ipb.wdata(i)'length , -- size of data elements in FIFO
386
387
FIFO_RSYNC => false , -- we NEED to read data asynchronously
387
388
FIFO_SAFE => false , -- no safe access required (ensured by FIFO-external logic)
388
- FULL_RESET => true -- map to FFs and add a dedicated reset
389
+ FULL_RESET => false -- no need for a full hardware reset
389
390
)
390
391
port map (
391
392
-- control --
@@ -1035,7 +1036,7 @@ begin
1035
1036
end case ;
1036
1037
1037
1038
when opcode_amo_c => -- atomic memory operation
1038
- if (exe_engine.ir(instr_funct3_msb_c downto instr_funct3_lsb_c) = "010" ) then
1039
+ if RISCV_ISA_Zaamo and (exe_engine.ir(instr_funct3_msb_c downto instr_funct3_lsb_c) = "010" ) then
1039
1040
case exe_engine.ir(instr_funct5_msb_c downto instr_funct5_lsb_c) is
1040
1041
when "00001" | "00000" | "00100" | "01100" | "01000" | "10000" | "10100" | "11000" | "11100" => illegal_cmd <= '0' ;
1041
1042
when others => illegal_cmd <= '1' ;
@@ -1332,6 +1333,7 @@ begin
1332
1333
-- External CSR Interface -----------------------------------------------------------------
1333
1334
-- -------------------------------------------------------------------------------------------
1334
1335
xcsr_we_o <= csr.we;
1336
+ xcsr_re_o <= '1' when (exe_engine.state = EX_SYSTEM) else '0' ;
1335
1337
xcsr_addr_o <= csr.addr;
1336
1338
xcsr_wdata_o <= csr.wdata;
1337
1339
0 commit comments