[sim/VUnit] make both UARTs visible

Author: umarcor

sim/neorv32_tb.vhd

@@ -149,13 +149,15 @@ architecture neorv32_tb_rtl of neorv32_tb is
   signal ext_mem_a, ext_mem_b, ext_mem_c : ext_mem_t;
 
   constant uart0_rx_logger : logger_t := get_logger("UART0.RX");
+  constant uart1_rx_logger : logger_t := get_logger("UART1.RX");
 
 begin
   test_runner : process
   begin
     test_runner_setup(runner, runner_cfg);
     -- Show passing checks for UART0 on the display (stdout)
     show(uart0_rx_logger, display_handler, pass);
+    show(uart1_rx_logger, display_handler, pass);
     wait for 35 ms; -- Just wait for all UART output to be produced
     test_runner_cleanup(runner);
   end process;
@@ -331,7 +333,7 @@ begin
 
     uart1_checker: entity work.uart_rx
       generic map (
-        logger => get_logger("uart1.rx"),
+        logger => uart1_rx_logger,
         expected => uart1_expectation,
         uart_baud_val_c => uart1_baud_val_c)
       port map (