🚀 preparing release v1.11.6

Author: stnolting

CHANGELOG.md

@@ -29,6 +29,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
 
 | Date | Version | Comment | Ticket |
 |:----:|:-------:|:--------|:------:|
+| 02.06.2025 | [**:rocket:1.11.6**](https://github.com/stnolting/neorv32/releases/tag/v1.11.6) | **New release** | |
 | 01.06.2025 | 1.11.5.9 | :test_tube: add optional output registers for IMEM & DMEM to improve FPGA mapping/timing results | [#1281](https://github.com/stnolting/neorv32/pull/1281) |
 | 31.05.2025 | 1.11.5.8 | :warning: rename IMEM/DMEM configuration generics | [#1280](https://github.com/stnolting/neorv32/pull/1280) |
 | 31.05.2025 | 1.11.5.7 | :test_tube: rework DMA controller | [#1279](https://github.com/stnolting/neorv32/pull/1279) |

docs/attrs.adoc

@@ -2,7 +2,7 @@
 :email: [email protected]
 :keywords: neorv32, risc-v, riscv, rv32, fpga, soft-core, vhdl, microcontroller, cpu, soc, processor, gcc, openocd, gdb, verilog, rtl, asip, asic
 :description: A size-optimized, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
-:revnumber: v1.11.5
+:revnumber: v1.11.6
 :icons: font
 :source-highlighter: highlight.js
 :imagesdir: ../figures

rtl/core/neorv32_package.vhd

@@ -29,7 +29,7 @@ package neorv32_package is
 
   -- Architecture Constants -----------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
-  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01110509"; -- hardware version
+  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01110600"; -- hardware version
   constant archid_c     : natural := 19; -- official RISC-V architecture ID
   constant XLEN         : natural := 32; -- native data path width
 

sw/svd/neorv32.svd

@@ -4,7 +4,7 @@
   <vendor>github.com/stnolting/neorv32</vendor>
   <name>neorv32</name>
   <series>RISC-V</series>
-  <version>1.11.5</version>
+  <version>1.11.6</version>
   <description>The NEORV32 RISC-V Processor</description>
 
   <!-- CPU core -->