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[rtl] minor edits and cleanups (#672)
2 parents 18d29f2 + fdb79e5 commit 46ef442

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‎CHANGELOG.md

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@@ -32,6 +32,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
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| Date (*dd.mm.yyyy*) | Version | Comment |
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|:-------------------:|:-------:|:--------|
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| 17.08.2023 | 1.8.7.9 | minor rtl edits and cleanups; [#672](https://github.com/stnolting/neorv32/pull/672) |
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| 13.08.2023 | 1.8.7.8 | :warning: constrain/optimize `mtval` and `mcounteren` CSRs; [#671](https://github.com/stnolting/neorv32/pull/671) |
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| 12.08.2023 | 1.8.7.7 | remove _unratified_ `Zicond` ISA extension; minor rtl code cleanups and optimizations; [#670](https://github.com/stnolting/neorv32/pull/670) |
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| 05.08.2023 | 1.8.7.6 | :bug: fix bug: HPM width configurations below 32 bit fail; [#665](https://github.com/stnolting/neorv32/pull/665) |

‎docs/datasheet/cpu_csr.adoc

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@@ -99,7 +99,7 @@ bits can actually be modified.
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| Name | Floating-point accrued exceptions
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| Address | `0x001`
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| Reset value | `0x00000000`
102-
| ISA | `Zicsr` + `Zfinx`
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| ISA | `Zicsr` & `Zfinx`
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| Description | FPU status flags.
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|=======================
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@@ -126,7 +126,7 @@ bits can actually be modified.
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| Name | Floating-point dynamic rounding mode
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| Address | `0x002`
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| Reset value | `0x00000000`
129-
| ISA | `Zicsr` + `Zfinx`
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| ISA | `Zicsr` & `Zfinx`
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| Description | The `frm` CSR is used to configure the rounding mode of the FPU.
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|=======================
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@@ -150,7 +150,7 @@ bits can actually be modified.
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| Name | Floating-point control and status register
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| Address | `0x003`
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| Reset value | `0x00000000`
153-
| ISA | `Zicsr` + `Zfinx`
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| ISA | `Zicsr` & `Zfinx`
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| Description | The `fcsr` provides combined access to the <<_fflags>> and <<_frm>> flags.
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|=======================
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@@ -179,7 +179,7 @@ bits can actually be modified.
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| Name | Machine environment configuration register
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| Address | `0x30a`
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| Reset value | `0x00000000`
182-
| ISA | `Zicsr` + `U`
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| ISA | `Zicsr` & `U`
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| Description | The features of this CSR are not implemented yet. The register is read-only and always returns zero.
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|=======================
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@@ -194,7 +194,7 @@ bits can actually be modified.
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| Name | Machine environment configuration register - high word
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| Address | `0x31a`
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| Reset value | `0x00000000`
197-
| ISA | `Zicsr` + `U`
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| ISA | `Zicsr` & `U`
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| Description | The features of this CSR are not implemented yet. The register is read-only and always returns zero.
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|=======================
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@@ -336,7 +336,7 @@ interrupt is triggered or an exception is raised.
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| Name | Machine counter enable
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| Address | `0x306`
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| Reset value | `0x00000000`
339-
| ISA | `Zicsr` + `U`
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| ISA | `Zicsr` & `U`
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| Description | The `mcounteren` CSR is used to constrain user-mode access to the CPU's counter CSRs.
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This CSR is also available if U mode is disabled, but the register is hardwired to all-zero in this case.
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|=======================
@@ -519,7 +519,7 @@ See section <<_pmp_isa_extension>> for more information.
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| Name | PMP region configuration registers
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| Address | `0x3a0` (`pmpcfg0`) ... `0x3a3` (`pmpcfg3`)
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| Reset value | `0x00000000`
522-
| ISA | `Zicsr` + `PMP`
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| ISA | `Zicsr` & `PMP`
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| Description | Configuration of physical memory protection regions. Each region provides an individual 8-bit array in these CSRs.
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|=======================
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@@ -549,7 +549,7 @@ The `pmpaddr*` CSRs are used to configure the region's address boundaries.
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| Name | Physical memory protection address registers
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| Address | `0x3b0` (`pmpaddr0`) ... `0x3bf` (`pmpaddr15`)
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| Reset value | `0x00000000`
552-
| ISA | `Zicsr` + `PMP`
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| ISA | `Zicsr` & `PMP`
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| Description | Region address configuration. The two MSBs of each CSR are hardwired to zero (= bits 33:32 of the physical address).
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|=======================
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@@ -586,7 +586,7 @@ if this instruction is actually going to retire or if it causes an exception.
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| Address | `0xc00` (`cycle`)
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| | `0xc80` (`cycleh`)
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| Reset value | `0x00000000`
589-
| ISA | `Zicsr` + `Zicntr`
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| ISA | `Zicsr` & `Zicntr`
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| Description | The `cycle[h]` CSRs are user-mode shadow copies of the according <<_mcycleh>> CSRs. The user-mode
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counter are read-only. Any write access will raise an illegal instruction exception.
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|=======================
@@ -603,7 +603,7 @@ counter are read-only. Any write access will raise an illegal instruction except
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| Address | `0xc02` (`instret`)
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| | `0xc82` (`instreth`)
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| Reset value | `0x00000000`
606-
| ISA | `Zicsr` + `Zicntr`
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| ISA | `Zicsr` & `Zicntr`
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| Description | The `instret[h]` CSRs are user-mode shadow copies of the according <<_minstreth>> CSRs. The user-mode
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counter are read-only. Any write access will raise an illegal instruction exception.
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|=======================
@@ -620,7 +620,7 @@ counter are read-only. Any write access will raise an illegal instruction except
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| Address | `0xb00` (`mcycle`)
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| | `0xb80` (`mcycleh`)
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| Reset value | `0x00000000`
623-
| ISA | `Zicsr` + `Zicntr`
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| ISA | `Zicsr` & `Zicntr`
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| Description | If not halted via the <<_mcountinhibit>> CSR the `cycle[h]` CSRs will increment with every active CPU clock
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cycle (CPU not in sleep mode). These registers are read/write only for machine-mode software.
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|=======================
@@ -637,7 +637,7 @@ cycle (CPU not in sleep mode). These registers are read/write only for machine-m
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| Address | `0xb02` (`minstret`)
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| | `0xb82` (`minstreth`)
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| Reset value | `0x00000000`
640-
| ISA | `Zicsr` + `Zicntr`
640+
| ISA | `Zicsr` & `Zicntr`
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| Description | If not halted via the <<_mcountinhibit>> CSR the `minstret[h]` CSRs will increment with every retired instruction.
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These registers are read/write only for machine-mode software
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|=======================
@@ -673,7 +673,7 @@ If `HPM_NUM_CNTS` is less than 64, all remaining MSB-aligned bits are hardwired
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| Name | Machine hardware performance monitor event select
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| Address | `0x233` (`mhpmevent3`) ... `0x32f` (`mhpmevent15`)
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| Reset value | `0x00000000`
676-
| ISA | `Zicsr` + `Zihpm`
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| ISA | `Zicsr` & `Zihpm`
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| Description | The value in these CSRs define the architectural events that cause an increment of the according `mhpmcounter*[h]` counter(s).
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All available events are listed in the table below. If more than one event is selected, the according counter will increment if _any_ of
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the enabled events is observed (logical OR). Note that the counter will only increment by 1 step per clock
@@ -715,7 +715,7 @@ cycle even if more than one trigger event is observed.
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| Address | `0xb03` (`mhpmcounter3`) ... `0xb0f` (mhpmcounter15)
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| | `0xb83` (`mhpmcounter3h`) ... `0xb8f` (`mhpmcounter15h`)
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| Reset value | `0x00000000`
718-
| ISA | `Zicsr` + `Zihpm`
718+
| ISA | `Zicsr` & `Zihpm`
719719
| Description | If not halted via the <<_mcountinhibit>> CSR the HPM counter CSR(s) increment whenever a
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configured event from the according <<_mhpmevent>> CSR occurs. The counter registers are read/write for machine mode
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and are not accessible for lower-privileged software.
@@ -733,7 +733,7 @@ and are not accessible for lower-privileged software.
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| Address | `0xc03` (`hpmcounter3`) ... `0xc0f` (hpmcounter15)
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| | `0xc83` (`hpmcounter3h`) ... `0xc8f` (`hpmcounter15h`)
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| Reset value | `0x00000000`
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| ISA | `Zicsr` + `Zihpm`
736+
| ISA | `Zicsr` & `Zihpm`
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| Description | The `hpmcounter*[h]` are user-mode shadow copies of the according <<_mhpmcounterh>> CSRs. The user mode
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counter CSRs are read-only. Any write access will raise an illegal instruction exception.
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|=======================
@@ -872,7 +872,7 @@ outside of machine-mode will raise an illegal instruction exception.
872872
| Name | Machine extended isa and extensions register
873873
| Address | `0xfc0`
874874
| Reset value | `DEFINED`
875-
| ISA | `Zicsr` + `X`
875+
| ISA | `Zicsr` & `X`
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| Description | The `mxisa` CSRs is a NEORV32-specific read-only CSR that helps machine-mode software to
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discover ISA sub-extensions and CPU configuration options
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|=======================

‎docs/datasheet/software_rte.adoc

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@@ -13,7 +13,7 @@ default handlers can be overridden by the application code to install applicatio
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Using the RTE is **optional but highly recommended**. The RTE provides a simple and comfortable way of delegating
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traps to application-specific handlers while making sure that all traps (even though they are not explicitly used
1515
by the application) are handled correctly. Performance-optimized applications or embedded operating systems may
16-
not use the RTE at allin order to increase response time.
16+
not use the RTE at all in order to increase response time.
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1818

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==== RTE Operation
@@ -80,7 +80,20 @@ enum NEORV32_RTE_TRAP_enum {
8080
RTE_TRAP_MEI = 12, /**< Machine external interrupt */
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RTE_TRAP_FIRQ_0 = 13, /**< Fast interrupt channel 0 */
8282
RTE_TRAP_FIRQ_1 = 14, /**< Fast interrupt channel 1 */
83-
...
83+
RTE_TRAP_FIRQ_2 = 15, /**< Fast interrupt channel 2 */
84+
RTE_TRAP_FIRQ_3 = 16, /**< Fast interrupt channel 3 */
85+
RTE_TRAP_FIRQ_4 = 17, /**< Fast interrupt channel 4 */
86+
RTE_TRAP_FIRQ_5 = 18, /**< Fast interrupt channel 5 */
87+
RTE_TRAP_FIRQ_6 = 19, /**< Fast interrupt channel 6 */
88+
RTE_TRAP_FIRQ_7 = 20, /**< Fast interrupt channel 7 */
89+
RTE_TRAP_FIRQ_8 = 21, /**< Fast interrupt channel 8 */
90+
RTE_TRAP_FIRQ_9 = 22, /**< Fast interrupt channel 9 */
91+
RTE_TRAP_FIRQ_10 = 23, /**< Fast interrupt channel 10 */
92+
RTE_TRAP_FIRQ_11 = 24, /**< Fast interrupt channel 11 */
93+
RTE_TRAP_FIRQ_12 = 25, /**< Fast interrupt channel 12 */
94+
RTE_TRAP_FIRQ_13 = 26, /**< Fast interrupt channel 13 */
95+
RTE_TRAP_FIRQ_14 = 27, /**< Fast interrupt channel 14 */
96+
RTE_TRAP_FIRQ_15 = 28 /**< Fast interrupt channel 15 */
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----
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8699
The second argument `*handler` is the actual function that implements the user-defined trap handler.

‎rtl/core/neorv32_cpu.vhd

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@@ -62,7 +62,7 @@ entity neorv32_cpu is
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CPU_EXTENSION_RISCV_Zxcfu : boolean; -- implement custom (instr.) functions unit?
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CPU_EXTENSION_RISCV_Sdext : boolean; -- implement external debug mode extension?
6464
CPU_EXTENSION_RISCV_Sdtrig : boolean; -- implement trigger module extension?
65-
-- Extension Options --
65+
-- Tuning Options --
6666
FAST_MUL_EN : boolean; -- use DSPs for M extension's multiplier
6767
FAST_SHIFT_EN : boolean; -- use barrel shifter for shift operations
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-- Physical Memory Protection (PMP) --
@@ -323,7 +323,7 @@ begin
323323
CPU_EXTENSION_RISCV_Zmmul => CPU_EXTENSION_RISCV_Zmmul, -- implement multiply-only M sub-extension?
324324
CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx, -- implement 32-bit floating-point extension (using INT reg!)
325325
CPU_EXTENSION_RISCV_Zxcfu => CPU_EXTENSION_RISCV_Zxcfu, -- implement custom (instr.) functions unit?
326-
-- Extension Options --
326+
-- Tuning Options --
327327
FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for M extension's multiplier
328328
FAST_SHIFT_EN => FAST_SHIFT_EN -- use barrel shifter for shift operations
329329
)

‎rtl/core/neorv32_cpu_alu.vhd

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@@ -49,7 +49,7 @@ entity neorv32_cpu_alu is
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CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension?
5050
CPU_EXTENSION_RISCV_Zfinx : boolean; -- implement 32-bit floating-point extension (using INT reg!)
5151
CPU_EXTENSION_RISCV_Zxcfu : boolean; -- implement custom (instr.) functions unit?
52-
-- Extension Options --
52+
-- Tuning Options --
5353
FAST_MUL_EN : boolean; -- use DSPs for M extension's multiplier
5454
FAST_SHIFT_EN : boolean -- use barrel shifter for shift operations
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);

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