Skip to content

Commit c793bc1

Browse files
dojyorinfpistm
dojyorin
and
fpistm
committed
variant(H5): add generic generic H503RBTx support
Signed-off-by: dojyorin <[email protected]> Co-authored-by: Frederic Pillon <[email protected]>
1 parent 01e4f0c commit c793bc1

File tree

4 files changed

+233
-2
lines changed

4 files changed

+233
-2
lines changed

‎README.md‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -521,6 +521,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
521521

522522
| Status | Device(s) | Name | Release | Notes |
523523
| :----: | :-------: | ---- | :-----: | :---- |
524+
| :yellow_heart: | STM32H503RB | Generic Board | **2.7.0** | |
524525
| :green_heart: | STM32H563IIKxQ | Generic Board | *2.6.0* | |
525526
| :green_heart: | STM32H563ZG<br>STM32H563ZI | Generic Board | *2.6.0* | |
526527
| :green_heart: | STM32H573IIKxQ | Generic Board | *2.6.0* | |

‎boards.txt‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7204,6 +7204,14 @@ GenH5.build.flash_offset=0x0
72047204
GenH5.upload.maximum_size=0
72057205
GenH5.upload.maximum_data_size=0
72067206

7207+
# Generic H503RBTx
7208+
GenH5.menu.pnum.GENERIC_H503RBTX=Generic H503RBTx
7209+
GenH5.menu.pnum.GENERIC_H503RBTX.upload.maximum_size=131072
7210+
GenH5.menu.pnum.GENERIC_H503RBTX.upload.maximum_data_size=32768
7211+
GenH5.menu.pnum.GENERIC_H503RBTX.build.board=GENERIC_H503RBTX
7212+
GenH5.menu.pnum.GENERIC_H503RBTX.build.product_line=STM32H503xx
7213+
GenH5.menu.pnum.GENERIC_H503RBTX.build.variant=STM32H5xx/H503RBT
7214+
72077215
# Generic H563IIKxQ
72087216
GenH5.menu.pnum.GENERIC_H563IIKXQ=Generic H563IIKxQ
72097217
GenH5.menu.pnum.GENERIC_H563IIKXQ.upload.maximum_size=2097152

‎variants/STM32H5xx/H503RBT/generic_clock.c‎

Lines changed: 49 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -20,8 +20,55 @@
2020
*/
2121
WEAK void SystemClock_Config(void)
2222
{
23-
/* SystemClock_Config can be generated by STM32CubeMX */
24-
#warning "SystemClock_Config() is empty. Default clock at reset is used."
23+
RCC_OscInitTypeDef RCC_OscInitStruct = {};
24+
RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
25+
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {};
26+
27+
/* Configure the main internal regulator output voltage */
28+
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
29+
30+
while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
31+
32+
/* Initializes the RCC Oscillators according to the specified parameters
33+
* in the RCC_OscInitTypeDef structure.
34+
*/
35+
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_CSI;
36+
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
37+
RCC_OscInitStruct.CSIState = RCC_CSI_ON;
38+
RCC_OscInitStruct.CSICalibrationValue = RCC_CSICALIBRATION_DEFAULT;
39+
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
40+
RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_CSI;
41+
RCC_OscInitStruct.PLL.PLLM = 1;
42+
RCC_OscInitStruct.PLL.PLLN = 125;
43+
RCC_OscInitStruct.PLL.PLLP = 2;
44+
RCC_OscInitStruct.PLL.PLLQ = 2;
45+
RCC_OscInitStruct.PLL.PLLR = 2;
46+
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_2;
47+
RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE;
48+
RCC_OscInitStruct.PLL.PLLFRACN = 0;
49+
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
50+
Error_Handler();
51+
}
52+
/* Initializes the CPU, AHB and APB buses clocks */
53+
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
54+
| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2
55+
| RCC_CLOCKTYPE_PCLK3;
56+
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
57+
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
58+
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
59+
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
60+
RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1;
61+
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
62+
Error_Handler();
63+
}
64+
65+
/* Initializes the peripherals clock */
66+
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_USB;
67+
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
68+
PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_CSI;
69+
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
70+
Error_Handler();
71+
}
2572
}
2673

2774
#endif /* ARDUINO_GENERIC_* */

‎variants/STM32H5xx/H503RBT/ldscript.ld‎

Lines changed: 175 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,175 @@
1+
/*
2+
******************************************************************************
3+
**
4+
** @file : LinkerScript.ld
5+
**
6+
** @author : Auto-generated by STM32CubeIDE
7+
**
8+
** @brief : Linker script for STM32H503RBTx Device from STM32H5 series
9+
** 128Kbytes FLASH
10+
** 32Kbytes RAM
11+
**
12+
** Set heap size, stack size and stack location according
13+
** to application requirements.
14+
**
15+
** Set memory bank area and size if external memory is used
16+
**
17+
** Target : STMicroelectronics STM32
18+
**
19+
** Distribution: The file is distributed as is, without any warranty
20+
** of any kind.
21+
**
22+
******************************************************************************
23+
** @attention
24+
**
25+
** Copyright (c) 2021 STMicroelectronics.
26+
** All rights reserved.
27+
**
28+
** This software is licensed under terms that can be found in the LICENSE file
29+
** in the root directory of this software component.
30+
** If no LICENSE file comes with this software, it is provided AS-IS.
31+
**
32+
******************************************************************************
33+
*/
34+
35+
/* Entry Point */
36+
ENTRY(Reset_Handler)
37+
38+
/* Highest address of the user mode stack */
39+
_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
40+
41+
_Min_Heap_Size = 0x200; /* required amount of heap */
42+
_Min_Stack_Size = 0x400; /* required amount of stack */
43+
44+
/* Memories definition */
45+
MEMORY {
46+
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE
47+
FLASH ( rx) : ORIGIN = 0x08000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
48+
}
49+
50+
/* Sections */
51+
SECTIONS {
52+
/* The startup code into "FLASH" Rom type memory */
53+
.isr_vector : {
54+
. = ALIGN(4);
55+
KEEP(*(.isr_vector)) /* Startup code */
56+
. = ALIGN(4);
57+
} > FLASH
58+
59+
/* The program code and other data into "FLASH" Rom type memory */
60+
.text : {
61+
. = ALIGN(4);
62+
*(.text) /* .text sections (code) */
63+
*(.text*) /* .text* sections (code) */
64+
*(.glue_7) /* glue arm to thumb code */
65+
*(.glue_7t) /* glue thumb to arm code */
66+
*(.eh_frame)
67+
68+
KEEP(*(.init))
69+
KEEP(*(.fini))
70+
71+
. = ALIGN(4);
72+
_etext = .; /* define a global symbols at end of code */
73+
} > FLASH
74+
75+
/* Constant data into "FLASH" Rom type memory */
76+
.rodata : {
77+
. = ALIGN(4);
78+
*(.rodata) /* .rodata sections (constants, strings, etc.) */
79+
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
80+
. = ALIGN(4);
81+
} > FLASH
82+
83+
.ARM.extab : {
84+
. = ALIGN(4);
85+
*(.ARM.extab* .gnu.linkonce.armextab.*)
86+
. = ALIGN(4);
87+
} > FLASH
88+
89+
.ARM : {
90+
. = ALIGN(4);
91+
__exidx_start = .;
92+
*(.ARM.exidx*)
93+
__exidx_end = .;
94+
. = ALIGN(4);
95+
} > FLASH
96+
97+
.preinit_array : {
98+
. = ALIGN(4);
99+
PROVIDE_HIDDEN(__preinit_array_start = .);
100+
KEEP(*(.preinit_array*))
101+
PROVIDE_HIDDEN(__preinit_array_end = .);
102+
. = ALIGN(4);
103+
} > FLASH
104+
105+
.init_array : {
106+
. = ALIGN(4);
107+
PROVIDE_HIDDEN(__init_array_start = .);
108+
KEEP(*(SORT(.init_array.*)))
109+
KEEP(*(.init_array*))
110+
PROVIDE_HIDDEN(__init_array_end = .);
111+
. = ALIGN(4);
112+
} > FLASH
113+
114+
.fini_array : {
115+
. = ALIGN(4);
116+
PROVIDE_HIDDEN(__fini_array_start = .);
117+
KEEP(*(SORT(.fini_array.*)))
118+
KEEP(*(.fini_array*))
119+
PROVIDE_HIDDEN(__fini_array_end = .);
120+
. = ALIGN(4);
121+
} > FLASH
122+
123+
/* Used by the startup to initialize data */
124+
_sidata = LOADADDR(.data);
125+
126+
/* Initialized data sections into "RAM" Ram type memory */
127+
.data : {
128+
. = ALIGN(4);
129+
_sdata = .; /* create a global symbol at data start */
130+
*(.data) /* .data sections */
131+
*(.data*) /* .data* sections */
132+
*(.RamFunc) /* .RamFunc sections */
133+
*(.RamFunc*) /* .RamFunc* sections */
134+
135+
. = ALIGN(4);
136+
_edata = .; /* define a global symbol at data end */
137+
138+
} > RAM AT > FLASH
139+
140+
/* Uninitialized data section into "RAM" Ram type memory */
141+
. = ALIGN(4);
142+
.bss : {
143+
/* This is used by the startup in order to initialize the .bss section */
144+
_sbss = .; /* define a global symbol at bss start */
145+
__bss_start__ = _sbss;
146+
*(.bss)
147+
*(.bss*)
148+
*(COMMON)
149+
150+
. = ALIGN(4);
151+
_ebss = .; /* define a global symbol at bss end */
152+
__bss_end__ = _ebss;
153+
} > RAM
154+
155+
/* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
156+
._user_heap_stack : {
157+
. = ALIGN(8);
158+
PROVIDE(end = .);
159+
PROVIDE(_end = .);
160+
. = . + _Min_Heap_Size;
161+
. = . + _Min_Stack_Size;
162+
. = ALIGN(8);
163+
} > RAM
164+
165+
/* Remove information from the compiler libraries */
166+
/DISCARD/ : {
167+
libc.a (*)
168+
libm.a (*)
169+
libgcc.a (*)
170+
}
171+
172+
.ARM.attributes 0 : {
173+
*(.ARM.attributes)
174+
}
175+
}

0 commit comments

Comments
 (0)