add apb2 bus

Author: xoviat

src/rcc.rs

@@ -13,6 +13,7 @@ impl RccExt for RCC {
     fn constrain(self) -> Rcc {
         Rcc {
             apb1: APB1 { _0: () },
+            apb2: APB2 { _0: () },
             cfgr: CFGR {
                 hse: None,
                 hclk: None,
@@ -31,6 +32,9 @@ pub struct Rcc {
 
     /// Advanced Peripheral Bus 1 (APB1) registers
     pub apb1: APB1,
+
+    /// Advanced Peripheral Bus 2 (APB2) registers
+    pub apb2: APB2,
 }
 
 /// Advanced Peripheral Bus 1 (APB1) registers
@@ -65,6 +69,31 @@ impl APB1 {
     }
 }
 
+/// Advanced Peripheral Bus 2 (APB2) registers
+///
+/// Aquired through the `Rcc` registers:
+///
+/// ```rust
+/// let dp = pac::Peripherals::take().unwrap();
+/// let mut rcc = dp.RCC.constrain();
+/// function_that_uses_apb2(&mut rcc.apb2);
+/// ```
+pub struct APB2 {
+    _0: (),
+}
+
+impl APB2 {
+    pub(crate) fn enr(&mut self) -> &rcc::APB2ENR {
+        // NOTE(unsafe) this proxy grants exclusive access to this register
+        unsafe { &(*RCC::ptr()).apb2enr }
+    }
+
+    pub(crate) fn rstr(&mut self) -> &rcc::APB2RSTR {
+        // NOTE(unsafe) this proxy grants exclusive access to this register
+        unsafe { &(*RCC::ptr()).apb2rstr }
+    }
+}
+
 /// Built-in high speed clock frequency
 pub const HSI: u32 = 16_000_000; // Hz
 
@@ -547,6 +576,15 @@ impl GetBusFreq for APB1 {
     }
 }
 
+impl GetBusFreq for APB2 {
+    fn get_frequency(clocks: &Clocks) -> Hertz {
+        clocks.pclk2
+    }
+    fn get_timer_frequency(clocks: &Clocks) -> Hertz {
+        clocks.pclk2()
+    }
+}
+
 pub(crate) mod sealed {
     /// Bus associated to peripheral
     pub trait RccBus {