diff --git a/CHANGELOG.md b/CHANGELOG.md
index afc63b97..4c38547a 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -13,6 +13,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - LSB/MSB bit format selection for `SPI`
 - Support for CAN peripherals with the `bxcan` crate
 - Add DAC, UART4, UART5 clock in RCC for the f103 high density line
+- `start_raw` function and `arr`, `bsc` getters for more fine grained
+  control over the timer.
 
 ### Fixed
 - Fix > 2 byte i2c reads
diff --git a/src/timer.rs b/src/timer.rs
index f93b3dd2..c0f37df6 100644
--- a/src/timer.rs
+++ b/src/timer.rs
@@ -314,6 +314,15 @@ macro_rules! hal {
                     }
                 )?
 
+                /// Starts the timer in count down mode with user-defined prescaler and auto-reload register
+                pub fn start_raw(self, psc: u16, arr: u16) -> CountDownTimer<$TIMX>
+                {
+                    let Self { tim, clk } = self;
+                    let mut timer = CountDownTimer { tim, clk };
+                    timer.restart_raw(psc, arr);
+                    timer
+                }
+
                 /// Resets timer peripheral
                 #[inline(always)]
                 pub fn clocking_reset(&mut self, apb: &mut <$TIMX as RccBus>::Bus) {
@@ -347,6 +356,40 @@ macro_rules! hal {
                     }
                 }
 
+                /// Restarts the timer in count down mode with user-defined prescaler and auto-reload register
+                pub fn restart_raw(&mut self, psc: u16, arr: u16)
+                {
+                    // pause
+                    self.tim.cr1.modify(|_, w| w.cen().clear_bit());
+
+                    self.tim.psc.write(|w| w.psc().bits(psc) );
+
+                    // TODO: Remove this `allow` once this field is made safe for stm32f100
+                    #[allow(unused_unsafe)]
+                    self.tim.arr.write(|w| unsafe { w.arr().bits(arr) });
+
+                    // Trigger an update event to load the prescaler value to the clock
+                    self.reset();
+
+                    // start counter
+                    self.tim.cr1.modify(|_, w| w.cen().set_bit());
+                }
+
+                /// Retrieves the content of the prescaler register. The real prescaler is this value + 1.
+                pub fn psc(&self) -> u16 {
+                    self.tim.psc.read().psc().bits()
+                }
+
+                /// Retrieves the value of the auto-reload register.
+                pub fn arr(&self) -> u16 {
+                    self.tim.arr.read().arr().bits()
+                }
+
+                /// Retrieves the current timer counter value.
+                pub fn cnt(&self) -> u16 {
+                    self.tim.cnt.read().cnt().bits()
+                }
+
                 /// Stops the timer
                 pub fn stop(self) -> Timer<$TIMX> {
                     self.tim.cr1.modify(|_, w| w.cen().clear_bit());
@@ -399,21 +442,8 @@ macro_rules! hal {
                 where
                     T: Into<Hertz>,
                 {
-                    // pause
-                    self.tim.cr1.modify(|_, w| w.cen().clear_bit());
-
                     let (psc, arr) = compute_arr_presc(timeout.into().0, self.clk.0);
-                    self.tim.psc.write(|w| w.psc().bits(psc) );
-
-                    // TODO: Remove this `allow` once this field is made safe for stm32f100
-                    #[allow(unused_unsafe)]
-                    self.tim.arr.write(|w| unsafe { w.arr().bits(arr) });
-
-                    // Trigger an update event to load the prescaler value to the clock
-                    self.reset();
-
-                    // start counter
-                    self.tim.cr1.modify(|_, w| w.cen().set_bit());
+                    self.restart_raw(psc, arr);
                 }
 
                 fn wait(&mut self) -> nb::Result<(), Void> {