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Make rcc::APB1.enr(), rcc::APB1.rstr(), etc public #62

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skammer opened this issue May 4, 2019 · 1 comment
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Make rcc::APB1.enr(), rcc::APB1.rstr(), etc public #62

skammer opened this issue May 4, 2019 · 1 comment

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@skammer
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skammer commented May 4, 2019

When enabling standby mode, there is a need to set PWREN bit in APB1 ENR register.

Right now it can be achieved by calling constrain on rcc.bkp. https://github.com/stm32-rs/stm32f1xx-hal/blob/master/src/rcc.rs#L367

And while it does set the right bits in the right places, it enables other registers as well, which may to may not be desirable.

Ideally, I'd like to be able to do it manually:

rcc.apb1.enr().modify(|_r, w| {
    w.pwren().set_bit()
});

Or maybe just call a function that does it for me, something like what set_sleepdeep() does: https://github.com/rust-embedded/cortex-m/blob/master/src/peripheral/scb.rs#L585

rcc.apb1.set_pwren();

I'd be happy to provide a PR for that, I'm just not entirely sure which is the best way to approach this issue.

@TheZoq2
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TheZoq2 commented May 4, 2019

I too am kind of interested in standby mode, but the RCC is not the easiest thing to modify and get right. Exposing enr would allow you to break all abstractions since you could disable devices that are assumed to be enabled after initialisation.

Everything dealing with the backup domain was implemented after lots of discussions here #17.

Or maybe just call a function that does it for me, something like what set_sleepdeep() does: https://github.com/rust-embedded/cortex-m/blob/master/src/peripheral/scb.rs#L585

I think that might work, feel free to open a PR with something like that and we can probably discuss it further :)

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