FPGA - Transfer optimisation

[bartokon]

Hello,

@definelicht please take a look at this document: https://www.xilinx.com/html_docs/xilinx2020_1/vitis_doc/methodologyacceleratingapplications.html#yfz1555544741101

Also all input should be 512 bit width if possible:

https://github.com/Xilinx/Vitis_Accel_Examples/blob/master/performance/axi_burst_performance/details.rst

I think FPGA kernels are missing some performance because of no cache buffers. If not, please prove me wrong :)

Take care,
BR

[definelicht]

Hi Bartek,

I agree with both of these points. Keep in mind that DaCe itself is a programming model and optimization framework, and both of these optimizations can be implemented with SDFGs :-) We just don't have everything automated, so it must be implemented in the SDFG. However, the StreamingMemory transformation does somewhat do what you want for cases where it matches.

Regarding 512-bit reads, we have the Gearbox node, which lets you easily convert between 512-bit and lower widths. There is also an effort to integrate this into the streaming memory transformation.

(disclaimer: I no longer work at the university, and will only have time to contribute basic maintenance in the future, so the rest of the team are responsible for larger upgrades)