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| 1 | +From a16c819d0896932ca52006fc0ba1c977bd2ad7f6 Mon Sep 17 00:00:00 2001 |
| 2 | +From: Vadim Pasternak < [email protected]> |
| 3 | +Date: Wed, 26 Jan 2022 17:16:26 +0200 |
| 4 | +Subject: [PATCH platform backport v5.10 03/10] mlx-platform: Add support for |
| 5 | + systems equipped with two ASICs |
| 6 | + |
| 7 | +Motivation is to support new systems equipped with two ASICs. |
| 8 | + |
| 9 | +Extend driver with: |
| 10 | +- The second ASIC health event. |
| 11 | +- Per ASIC reset control, triggering reset of ASIC internal resources |
| 12 | + and restarting ASIC initialization flow. |
| 13 | + |
| 14 | +Signed-off-by: Vadim Pasternak < [email protected]> |
| 15 | +Reviewed-by: Oleksandr Shamray < [email protected]> |
| 16 | +--- |
| 17 | + drivers/platform/x86/mlx-platform.c | 52 ++++++++++++++++++++++++++++- |
| 18 | + 1 file changed, 51 insertions(+), 1 deletion(-) |
| 19 | + |
| 20 | +diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c |
| 21 | +index a74fcd9d1..cbe9eab34 100644 |
| 22 | +--- a/drivers/platform/x86/mlx-platform.c |
| 23 | ++++ b/drivers/platform/x86/mlx-platform.c |
| 24 | +@@ -34,6 +34,7 @@ |
| 25 | + #define MLXPLAT_CPLD_LPC_REG_CPLD3_PN1_OFFSET 0x09 |
| 26 | + #define MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET 0x0a |
| 27 | + #define MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET 0x0b |
| 28 | ++#define MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET 0x19 |
| 29 | + #define MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET 0x1c |
| 30 | + #define MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET 0x1d |
| 31 | + #define MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET 0x1e |
| 32 | +@@ -69,6 +70,9 @@ |
| 33 | + #define MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET 0x50 |
| 34 | + #define MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET 0x51 |
| 35 | + #define MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET 0x52 |
| 36 | ++#define MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET 0x53 |
| 37 | ++#define MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET 0x54 |
| 38 | ++#define MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET 0x55 |
| 39 | + #define MLXPLAT_CPLD_LPC_REG_AGGRLC_OFFSET 0x56 |
| 40 | + #define MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET 0x57 |
| 41 | + #define MLXPLAT_CPLD_LPC_REG_PSU_OFFSET 0x58 |
| 42 | +@@ -193,6 +197,7 @@ |
| 43 | + MLXPLAT_CPLD_AGGR_MASK_LC_ACT | \ |
| 44 | + MLXPLAT_CPLD_AGGR_MASK_LC_SDWN) |
| 45 | + #define MLXPLAT_CPLD_LOW_AGGR_MASK_LOW 0xc1 |
| 46 | ++#define MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2 BIT(2) |
| 47 | + #define MLXPLAT_CPLD_LOW_AGGR_MASK_I2C BIT(6) |
| 48 | + #define MLXPLAT_CPLD_PSU_MASK GENMASK(1, 0) |
| 49 | + #define MLXPLAT_CPLD_PWR_MASK GENMASK(1, 0) |
| 50 | +@@ -589,6 +594,15 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_asic_items_data[] = { |
| 51 | + }, |
| 52 | + }; |
| 53 | + |
| 54 | ++static struct mlxreg_core_data mlxplat_mlxcpld_default_asic2_items_data[] = { |
| 55 | ++ { |
| 56 | ++ .label = "asic2", |
| 57 | ++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET, |
| 58 | ++ .mask = MLXPLAT_CPLD_ASIC_MASK, |
| 59 | ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, |
| 60 | ++ }, |
| 61 | ++}; |
| 62 | ++ |
| 63 | + static struct mlxreg_core_item mlxplat_mlxcpld_default_items[] = { |
| 64 | + { |
| 65 | + .data = mlxplat_mlxcpld_default_psu_items_data, |
| 66 | +@@ -1252,6 +1266,15 @@ static struct mlxreg_core_item mlxplat_mlxcpld_ext_items[] = { |
| 67 | + .inversed = 0, |
| 68 | + .health = true, |
| 69 | + }, |
| 70 | ++ { |
| 71 | ++ .data = mlxplat_mlxcpld_default_asic2_items_data, |
| 72 | ++ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, |
| 73 | ++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET, |
| 74 | ++ .mask = MLXPLAT_CPLD_ASIC_MASK, |
| 75 | ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic2_items_data), |
| 76 | ++ .inversed = 0, |
| 77 | ++ .health = true, |
| 78 | ++ } |
| 79 | + }; |
| 80 | + |
| 81 | + static |
| 82 | +@@ -1261,7 +1284,7 @@ struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ext_data = { |
| 83 | + .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, |
| 84 | + .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, |
| 85 | + .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, |
| 86 | +- .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, |
| 87 | ++ .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW | MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2, |
| 88 | + }; |
| 89 | + |
| 90 | + static struct mlxreg_core_data mlxplat_mlxcpld_modular_pwr_items_data[] = { |
| 91 | +@@ -3075,6 +3098,18 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { |
| 92 | + .bit = GENMASK(7, 0), |
| 93 | + .mode = 0444, |
| 94 | + }, |
| 95 | ++ { |
| 96 | ++ .label = "asic_reset", |
| 97 | ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET, |
| 98 | ++ .mask = GENMASK(7, 0) & ~BIT(3), |
| 99 | ++ .mode = 0644, |
| 100 | ++ }, |
| 101 | ++ { |
| 102 | ++ .label = "asic2_reset", |
| 103 | ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET, |
| 104 | ++ .mask = GENMASK(7, 0) & ~BIT(2), |
| 105 | ++ .mode = 0444, |
| 106 | ++ }, |
| 107 | + { |
| 108 | + .label = "reset_long_pb", |
| 109 | + .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, |
| 110 | +@@ -3214,6 +3249,13 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { |
| 111 | + .bit = 1, |
| 112 | + .mode = 0444, |
| 113 | + }, |
| 114 | ++ { |
| 115 | ++ .label = "asic2_health", |
| 116 | ++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET, |
| 117 | ++ .mask = MLXPLAT_CPLD_ASIC_MASK, |
| 118 | ++ .bit = 1, |
| 119 | ++ .mode = 0444, |
| 120 | ++ }, |
| 121 | + { |
| 122 | + .label = "fan_dir", |
| 123 | + .reg = MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION, |
| 124 | +@@ -4254,6 +4296,8 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) |
| 125 | + case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET: |
| 126 | + case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET: |
| 127 | + case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET: |
| 128 | ++ case MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET: |
| 129 | ++ case MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET: |
| 130 | + case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET: |
| 131 | + case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET: |
| 132 | + case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET: |
| 133 | +@@ -4346,6 +4390,9 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) |
| 134 | + case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET: |
| 135 | + case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET: |
| 136 | + case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET: |
| 137 | ++ case MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET: |
| 138 | ++ case MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET: |
| 139 | ++ case MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET: |
| 140 | + case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET: |
| 141 | + case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET: |
| 142 | + case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET: |
| 143 | +@@ -4473,6 +4520,9 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) |
| 144 | + case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET: |
| 145 | + case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET: |
| 146 | + case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET: |
| 147 | ++ case MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET: |
| 148 | ++ case MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET: |
| 149 | ++ case MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET: |
| 150 | + case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET: |
| 151 | + case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET: |
| 152 | + case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET: |
| 153 | +-- |
| 154 | +2.20.1 |
| 155 | + |
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