From b0dec2c92c570fa9d7d04d80aca381fd360ff52c Mon Sep 17 00:00:00 2001 From: Sudharsan Dhamal Gopalarathnam Date: Wed, 10 Apr 2024 17:15:15 -0700 Subject: [PATCH] Intgerate HW-MGMT 7.0030.3008 Changes (#391) ## Patch List * 0042-hwmon-mlxreg-fan-Add-support-for-new-flavour-of-capa.patch : * 0044-leds-mlxreg-Add-support-for-new-flavour-of-capabilit.patch : * 0045-leds-mlxreg-Remove-code-for-amber-LED-colour.patch : * 0046-Extend-driver-to-support-Infineon-Digital-Multi-phas.patch : * 0047-dt-bindings-trivial-devices-Add-infineon-xdpe1a2g7.patch : * 0048-hwmon-pmbus-Add-support-for-MPS-Multi-phase-mp2891-c.patch : * 0049-dt-bindings-trivial-devices-Add-mps-mp2891.patch : * 0050-leds-mlxreg-Skip-setting-LED-color-during-initializa.patch : * 0053-platform-mellanox-Add-support-for-dynamic-I2C-channe.patch : * 0054-platform-mellanox-Introduce-support-for-switches-equ.patch : * 0055-mellanox-Relocate-mlx-platform-driver.patch : * 0087-platform-mellanox-indicate-deferred-I2C-bus-creation.patch : * 8000-mlxsw-Use-weak-reverse-dependencies-for-firmware-fla.patch : * 8004-mlxsw-minimal-Downstream-Ignore-error-reading-SPAD-r.patch : * 8010-mlxsw-i2c-Downstream-Add-retry-mechanism-for-failed-.patch : * 8011-mlxsw-minimal-Downstream-Disable-ethtool-interface.patch : --- ...-Add-support-for-new-flavour-of-capa.patch | 65 ++ ...support-for-new-flavour-of-capabilit.patch | 62 ++ ...reg-Remove-code-for-amber-LED-colour.patch | 47 ++ ...-support-Infineon-Digital-Multi-phas.patch | 37 ++ ...ivial-devices-Add-infineon-xdpe1a2g7.patch | 29 + ...support-for-MPS-Multi-phase-mp2891-c.patch | 563 ++++++++++++++++++ ...dings-trivial-devices-Add-mps-mp2891.patch | 30 + ...-setting-LED-color-during-initializa.patch | 39 ++ ...x-Add-support-for-dynamic-I2C-channe.patch | 159 +++++ ...x-Introduce-support-for-switches-equ.patch | 312 ++++++++++ ...ellanox-Relocate-mlx-platform-driver.patch | 98 +++ ...I-Add-new-attribute-for-mlxreg-io-sy.patch | 74 --- ...e-struct-pinfunction-and-PINCTRL_PIN.patch | 59 -- ...rl-mlxbf3-Add-pinctrl-driver-support.patch | 393 ------------ ...-gpio-mlxbf3-Add-gpio-driver-support.patch | 314 ---------- ...et-varaiable-mlxbf3_pmx_funcs-storag.patch | 35 -- ...x-indicate-deferred-I2C-bus-creation.patch | 31 + ...everse-dependencies-for-firmware-fla.patch | 34 ++ ...wnstream-Ignore-error-reading-SPAD-r.patch | 36 ++ ...ream-Add-retry-mechanism-for-failed-.patch | 128 ++++ ...Downstream-Disable-ethtool-interface.patch | 51 ++ patch/kconfig-inclusions | 5 +- patch/series | 21 +- 23 files changed, 1739 insertions(+), 883 deletions(-) create mode 100644 patch/0042-hwmon-mlxreg-fan-Add-support-for-new-flavour-of-capa.patch create mode 100644 patch/0044-leds-mlxreg-Add-support-for-new-flavour-of-capabilit.patch create mode 100644 patch/0045-leds-mlxreg-Remove-code-for-amber-LED-colour.patch create mode 100644 patch/0046-Extend-driver-to-support-Infineon-Digital-Multi-phas.patch create mode 100644 patch/0047-dt-bindings-trivial-devices-Add-infineon-xdpe1a2g7.patch create mode 100644 patch/0048-hwmon-pmbus-Add-support-for-MPS-Multi-phase-mp2891-c.patch create mode 100644 patch/0049-dt-bindings-trivial-devices-Add-mps-mp2891.patch create mode 100644 patch/0050-leds-mlxreg-Skip-setting-LED-color-during-initializa.patch create mode 100644 patch/0053-platform-mellanox-Add-support-for-dynamic-I2C-channe.patch create mode 100644 patch/0054-platform-mellanox-Introduce-support-for-switches-equ.patch create mode 100644 patch/0055-mellanox-Relocate-mlx-platform-driver.patch delete mode 100644 patch/0057-Documentation-ABI-Add-new-attribute-for-mlxreg-io-sy.patch delete mode 100644 patch/0061-pinctrl-Introduce-struct-pinfunction-and-PINCTRL_PIN.patch delete mode 100644 patch/0062-pinctrl-mlxbf3-Add-pinctrl-driver-support.patch delete mode 100644 patch/0063-gpio-mlxbf3-Add-gpio-driver-support.patch delete mode 100644 patch/0064-pinctrl-mlxbf3-set-varaiable-mlxbf3_pmx_funcs-storag.patch create mode 100644 patch/0087-platform-mellanox-indicate-deferred-I2C-bus-creation.patch create mode 100644 patch/8000-mlxsw-Use-weak-reverse-dependencies-for-firmware-fla.patch create mode 100644 patch/8004-mlxsw-minimal-Downstream-Ignore-error-reading-SPAD-r.patch create mode 100644 patch/8010-mlxsw-i2c-Downstream-Add-retry-mechanism-for-failed-.patch create mode 100644 patch/8011-mlxsw-minimal-Downstream-Disable-ethtool-interface.patch diff --git a/patch/0042-hwmon-mlxreg-fan-Add-support-for-new-flavour-of-capa.patch b/patch/0042-hwmon-mlxreg-fan-Add-support-for-new-flavour-of-capa.patch new file mode 100644 index 000000000000..df8454321a83 --- /dev/null +++ b/patch/0042-hwmon-mlxreg-fan-Add-support-for-new-flavour-of-capa.patch @@ -0,0 +1,65 @@ +From bb46d45ce13c8faf9c2ab57b945c3a3adc587918 Mon Sep 17 00:00:00 2001 +From: Vadim Pasternak +Date: Sun, 23 Jul 2023 06:26:09 +0000 +Subject: [PATCH backport 6.1.42 42/85] hwmon: (mlxreg-fan) Add support for new + flavour of capability register + +FAN platform data is common across the various systems, while fan +driver should be able to apply only the fan instances relevant +to specific system. + +For example, platform data might contain descriptions for fan1, +fan2, ..., fan{n}, while some systems equipped with all 'n' fans, +others with less. +Also, on some systems fan drawer can be equipped with several +tachometers and on others only with one. + +For detection of the real number of equipped drawers and tachometers +special capability registers are used. +These registers used to indicate presence of drawers and tachometers +through the bitmap. + +For some new big modular systems this register will provide presence +data by counter. + +Use slot parameter to distinct whether capability register contains +bitmask or counter. + +Signed-off-by: Vadim Pasternak +--- + drivers/hwmon/mlxreg-fan.c | 12 ++++++++++-- + 1 file changed, 10 insertions(+), 2 deletions(-) + +diff --git a/drivers/hwmon/mlxreg-fan.c b/drivers/hwmon/mlxreg-fan.c +index 96017cc8da7e..dad94d2892b2 100644 +--- a/drivers/hwmon/mlxreg-fan.c ++++ b/drivers/hwmon/mlxreg-fan.c +@@ -390,7 +390,7 @@ static int mlxreg_fan_connect_verify(struct mlxreg_fan *fan, + return err; + } + +- return !!(regval & data->bit); ++ return data->slot ? (data->slot <= regval ? 1 : 0) : !!(regval & data->bit); + } + + static int mlxreg_pwm_connect_verify(struct mlxreg_fan *fan, +@@ -527,7 +527,15 @@ static int mlxreg_fan_config(struct mlxreg_fan *fan, + return err; + } + +- drwr_avail = hweight32(regval); ++ /* ++ * The number of drawers could be specified in registers by counters for newer ++ * systems, or by bitmasks for older systems. In case the data is provided by ++ * counter, it is indicated through 'version' field. ++ */ ++ if (pdata->version) ++ drwr_avail = regval; ++ else ++ drwr_avail = hweight32(regval); + if (!tacho_avail || !drwr_avail || tacho_avail < drwr_avail) { + dev_err(fan->dev, "Configuration is invalid: drawers num %d tachos num %d\n", + drwr_avail, tacho_avail); +-- +2.20.1 + diff --git a/patch/0044-leds-mlxreg-Add-support-for-new-flavour-of-capabilit.patch b/patch/0044-leds-mlxreg-Add-support-for-new-flavour-of-capabilit.patch new file mode 100644 index 000000000000..225ef9b30a17 --- /dev/null +++ b/patch/0044-leds-mlxreg-Add-support-for-new-flavour-of-capabilit.patch @@ -0,0 +1,62 @@ +From 46c4b0cdf2a3abe321e137bcb87e5639c39fd655 Mon Sep 17 00:00:00 2001 +From: Vadim Pasternak +Date: Thu, 20 Jul 2023 11:01:56 +0000 +Subject: [PATCH backport 6.1.42 44/85] leds: mlxreg: Add support for new + flavour of capability register + +LED platform data is common across the various systems, while LED +driver should be able to apply only the LED instances relevant +to specific system. + +For example, platform data might contain descriptions for fan1, +fan2, ..., fan{n} LEDs, while some systems equipped with all 'n' fan +LEDs, others with less. + +For detection of the real number of equipped LEDs special capability +register is used. +This register used to indicate presence of LED through the bitmap. + +For some new big modular systems this register will provide presence +data by counter. + +Use slot parameter to distinct whether capability register contains +bitmask or counter. + +Signed-off-by: Vadim Pasternak +--- + drivers/leds/leds-mlxreg.c | 12 +++++++++--- + 1 file changed, 9 insertions(+), 3 deletions(-) + +diff --git a/drivers/leds/leds-mlxreg.c b/drivers/leds/leds-mlxreg.c +index b7855c93bd72..063a9cb50a2b 100644 +--- a/drivers/leds/leds-mlxreg.c ++++ b/drivers/leds/leds-mlxreg.c +@@ -206,16 +206,22 @@ static int mlxreg_led_config(struct mlxreg_led_priv_data *priv) + dev_err(&priv->pdev->dev, "Failed to query capability register\n"); + return err; + } +- if (!(regval & data->bit)) ++ /* ++ * If slot is specified - validate if slot is equipped on system. ++ * In case slot is specified in platform data, capability register ++ * comtains the counter of untits. ++ */ ++ if (data->slot && data->slot > regval) ++ continue; ++ else if (!(regval & data->bit)) + continue; + /* + * Field "bit" can contain one capability bit in 0 byte + * and offset bit in 1-3 bytes. Clear capability bit and +- * keep only offset bit. ++ * contains the counter of units. + */ + data->bit &= MLXREG_LED_CAPABILITY_CLEAR; + } +- + led_cdev = &led_data->led_cdev; + led_data->data_parent = priv; + if (strstr(data->label, "red") || +-- +2.20.1 + diff --git a/patch/0045-leds-mlxreg-Remove-code-for-amber-LED-colour.patch b/patch/0045-leds-mlxreg-Remove-code-for-amber-LED-colour.patch new file mode 100644 index 000000000000..a20c6183bc65 --- /dev/null +++ b/patch/0045-leds-mlxreg-Remove-code-for-amber-LED-colour.patch @@ -0,0 +1,47 @@ +From af93d2527b5af3f2e53507c7e35bcd9c9bd521cb Mon Sep 17 00:00:00 2001 +From: Vadim Pasternak +Date: Thu, 20 Jul 2023 11:17:31 +0000 +Subject: [PATCH backport 6.1.42 45/85] leds: mlxreg: Remove code for amber LED + colour + +Remove unused code for amber LED colour. + +In case system LED color is "green", "orange" or "amber" same code is +to be used for colour setting. + +Signed-off-by: Vadim Pasternak +--- + drivers/leds/leds-mlxreg.c | 8 ++------ + 1 file changed, 2 insertions(+), 6 deletions(-) + +diff --git a/drivers/leds/leds-mlxreg.c b/drivers/leds/leds-mlxreg.c +index 063a9cb50a2b..215132f67c07 100644 +--- a/drivers/leds/leds-mlxreg.c ++++ b/drivers/leds/leds-mlxreg.c +@@ -19,7 +19,6 @@ + #define MLXREG_LED_IS_OFF 0x00 /* Off */ + #define MLXREG_LED_RED_SOLID 0x05 /* Solid red */ + #define MLXREG_LED_GREEN_SOLID 0x0D /* Solid green */ +-#define MLXREG_LED_AMBER_SOLID 0x09 /* Solid amber */ + #define MLXREG_LED_BLINK_3HZ 167 /* ~167 msec off/on - HW support */ + #define MLXREG_LED_BLINK_6HZ 83 /* ~83 msec off/on - HW support */ + #define MLXREG_LED_CAPABILITY_CLEAR GENMASK(31, 8) /* Clear mask */ +@@ -224,13 +223,10 @@ static int mlxreg_led_config(struct mlxreg_led_priv_data *priv) + } + led_cdev = &led_data->led_cdev; + led_data->data_parent = priv; +- if (strstr(data->label, "red") || +- strstr(data->label, "orange")) { ++ if (strstr(data->label, "red") || strstr(data->label, "orange") || ++ strstr(data->label, "amber")) { + brightness = LED_OFF; + led_data->base_color = MLXREG_LED_RED_SOLID; +- } else if (strstr(data->label, "amber")) { +- brightness = LED_OFF; +- led_data->base_color = MLXREG_LED_AMBER_SOLID; + } else { + brightness = LED_OFF; + led_data->base_color = MLXREG_LED_GREEN_SOLID; +-- +2.20.1 + diff --git a/patch/0046-Extend-driver-to-support-Infineon-Digital-Multi-phas.patch b/patch/0046-Extend-driver-to-support-Infineon-Digital-Multi-phas.patch new file mode 100644 index 000000000000..7d242bac5454 --- /dev/null +++ b/patch/0046-Extend-driver-to-support-Infineon-Digital-Multi-phas.patch @@ -0,0 +1,37 @@ +From 276c9eae3cf83bb65c575b423c785d0ff37b6da0 Mon Sep 17 00:00:00 2001 +From: Vadim Pasternak +Date: Mon, 17 Jul 2023 15:40:08 +0000 +Subject: [PATCH backport 6.1.42 46/85] Extend driver to support Infineon + Digital Multi-phase XDPE1A2G7 device. + +From telemetry perspective device is almost the same as XDPE15284, but +does not support READ_EIN (86h) and READ_EOUT (87h) commands. + +Signed-off-by: Vadim Pasternak +--- + drivers/hwmon/pmbus/xdpe152c4.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/hwmon/pmbus/xdpe152c4.c b/drivers/hwmon/pmbus/xdpe152c4.c +index b8a36ef73e45..1ef1141ba537 100644 +--- a/drivers/hwmon/pmbus/xdpe152c4.c ++++ b/drivers/hwmon/pmbus/xdpe152c4.c +@@ -44,6 +44,7 @@ static int xdpe152_probe(struct i2c_client *client) + } + + static const struct i2c_device_id xdpe152_id[] = { ++ {"xdpe1a2g7", 0}, + {"xdpe152c4", 0}, + {"xdpe15284", 0}, + {} +@@ -52,6 +53,7 @@ static const struct i2c_device_id xdpe152_id[] = { + MODULE_DEVICE_TABLE(i2c, xdpe152_id); + + static const struct of_device_id __maybe_unused xdpe152_of_match[] = { ++ {.compatible = "infineon,xdpe1a2g7"}, + {.compatible = "infineon,xdpe152c4"}, + {.compatible = "infineon,xdpe15284"}, + {} +-- +2.20.1 + diff --git a/patch/0047-dt-bindings-trivial-devices-Add-infineon-xdpe1a2g7.patch b/patch/0047-dt-bindings-trivial-devices-Add-infineon-xdpe1a2g7.patch new file mode 100644 index 000000000000..cafc9b58d6b2 --- /dev/null +++ b/patch/0047-dt-bindings-trivial-devices-Add-infineon-xdpe1a2g7.patch @@ -0,0 +1,29 @@ +From 62520e9d0ab641b36fb770477792073e6aad4d54 Mon Sep 17 00:00:00 2001 +From: Vadim Pasternak +Date: Mon, 17 Jul 2023 16:24:58 +0000 +Subject: [PATCH backport 6.1.42 47/85] dt-bindings: trivial-devices: Add + infineon,xdpe1a2g7 + +Add new Infineon Multi-phase Digital VR Controller xdpe1a2g7 + +Signed-off-by: Vadim Pasternak +--- + Documentation/devicetree/bindings/trivial-devices.yaml | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/Documentation/devicetree/bindings/trivial-devices.yaml b/Documentation/devicetree/bindings/trivial-devices.yaml +index 61746755c107..7637390dfe09 100644 +--- a/Documentation/devicetree/bindings/trivial-devices.yaml ++++ b/Documentation/devicetree/bindings/trivial-devices.yaml +@@ -145,6 +145,8 @@ properties: + - infineon,tlv493d-a1b6 + # Infineon Multi-phase Digital VR Controller xdpe11280 + - infineon,xdpe11280 ++ # Infineon Multi-phase Digital VR Controller xdpe1a2g7 ++ - infineon,xdpe1a2g7 + # Infineon Multi-phase Digital VR Controller xdpe12254 + - infineon,xdpe12254 + # Infineon Multi-phase Digital VR Controller xdpe12284 +-- +2.20.1 + diff --git a/patch/0048-hwmon-pmbus-Add-support-for-MPS-Multi-phase-mp2891-c.patch b/patch/0048-hwmon-pmbus-Add-support-for-MPS-Multi-phase-mp2891-c.patch new file mode 100644 index 000000000000..860a7d220adf --- /dev/null +++ b/patch/0048-hwmon-pmbus-Add-support-for-MPS-Multi-phase-mp2891-c.patch @@ -0,0 +1,563 @@ +From c8a04a4c79a9fb99215e93884ff76b89e9947275 Mon Sep 17 00:00:00 2001 +From: Vadim Pasternak +Date: Thu, 13 Jul 2023 06:16:53 +0000 +Subject: [PATCH backport 6.1.42 48/85] hwmon: (pmbus) Add support for MPS + Multi-phase mp2891 controller +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Introduce driver for dual-loop, digital, multi-phase controller MP2891 from +Monolithic Power Systems, Inc. (MPS) vendor. + +The MP2891 can work with MPS’s Intelli-PhaseTM products to complete the +multi-phase voltage regulator (VR) solution with minimal external +components. + +This device supports: +- Two power rails. +- Programmable Multi-Phase up to 16 Phases on rail 1, and a maximum of 8 + phases on rail 2. + +Signed-off-by: Vadim Pasternak +--- + Documentation/hwmon/mp2891.rst | 128 ++++++++++++ + drivers/hwmon/pmbus/Kconfig | 9 + + drivers/hwmon/pmbus/Makefile | 1 + + drivers/hwmon/pmbus/mp2891.c | 357 +++++++++++++++++++++++++++++++++ + 4 files changed, 495 insertions(+) + create mode 100644 Documentation/hwmon/mp2891.rst + create mode 100644 drivers/hwmon/pmbus/mp2891.c + +diff --git a/Documentation/hwmon/mp2891.rst b/Documentation/hwmon/mp2891.rst +new file mode 100644 +index 000000000000..c4bda3d7ee8a +--- /dev/null ++++ b/Documentation/hwmon/mp2891.rst +@@ -0,0 +1,128 @@ ++.. SPDX-License-Identifier: GPL-2.0 ++ ++Kernel driver mp2891 ++==================== ++ ++Supported chips: ++ ++ * MPS MP2891 ++ ++ Prefix: 'mp2891' ++ ++Author: ++ ++ Vadim Pasternak ++ ++Description ++----------- ++ ++This driver implements support for Monolithic Power Systems, Inc. (MPS) ++vendor dual-loop, digital, multi-phase controller MP2891. ++The MP2891 can work with MPS’s Intelli-PhaseTM products to complete the ++multi-phase voltage regulator (VR) solution with minimal external components. ++ ++MP2891 is available in a QFN-56 (7mmx7mm) package. ++ ++This device supports: ++ ++- Two power rails. ++- Programmable Multi-Phase up to 16 Phases on rail 1, and a maximum of 8 phases ++ on rail 2. ++- PWM-VID Interface. ++- Two pages for telemetry. ++- Programmable pins for PMBus Address. ++- Ability to store and restore device configurations. ++- 200kHz to 3MHz Switching Frequency. ++- Automatic Loop Compensation. ++- Couple Inductor Mode. ++- Supports Multi-Configuration for 6 Different Applications. ++- Flexible Pulse-Width Modulation (PWM) Assignment for 2 Rails. ++- Automatic Phase-Shedding (APS) to Improve Overall Efficiency. ++- Phase-to-Phase Active Current Balancing with Configurable Offsets for Thermal ++ Balance. ++- Digital Load-Line Regulation. ++- Overclocking Mode by Adding Offset to VOUT. ++ ++Device complaint with: ++ ++- PMBus rev 1.3 interface. ++ ++Device supports direct format for reading output current, output voltage, ++input and output power and temperature. ++Device supports linear format for reading input voltage and input power. ++ ++The driver provides the next attributes for the current: ++ ++- for current out input and maximum alarm; ++- for phase current: input and label. ++ ++The driver exports the following attributes via the 'sysfs' files, where: ++ ++- 'n' is number of configured phases (from 1 to 10); ++- index 1 for "iout"; ++- indexes 2 ... 1 + n for phases. ++ ++**curr[1-{1+n}]_input** ++ ++**curr[1-{1+n}]_label** ++ ++**curr1_max** ++ ++**curr1_max_alarm** ++ ++The driver provides the next attributes for the voltage: ++ ++- for voltage in: input, low and high critical thresholds, low and high ++ critical alarms; ++- for voltage out: input and high alarm; ++ ++The driver exports the following attributes via the 'sysfs' files, where ++ ++**in1_crit** ++ ++**in1_crit_alarm** ++ ++**in1_input** ++ ++**in1_label** ++ ++**in1_min** ++ ++**in1_min_alarm** ++ ++**in2_alarm** ++ ++**in2_input** ++ ++**in2_label** ++ ++The driver provides the next attributes for the power: ++ ++- for power in alarm and input. ++- for power out: cap, cap alarm an input. ++ ++The driver exports the following attributes via the 'sysfs' files, where ++- indexes 1 for "pin"; ++- indexes 2 for "pout"; ++ ++**power1_alarm** ++ ++**power1_input** ++ ++**power1_label** ++ ++**power2_input** ++ ++**power2_label** ++ ++**power2_max** ++ ++**power2_max_alarm** ++ ++The driver provides the next attributes for the temperature: ++ ++**temp1_input** ++ ++**temp1_max** ++ ++**temp1_max_alarm** +diff --git a/drivers/hwmon/pmbus/Kconfig b/drivers/hwmon/pmbus/Kconfig +index 89668af67206..77d67344cee4 100644 +--- a/drivers/hwmon/pmbus/Kconfig ++++ b/drivers/hwmon/pmbus/Kconfig +@@ -299,6 +299,15 @@ config SENSORS_MP2888 + This driver can also be built as a module. If so, the module will + be called mp2888. + ++config SENSORS_MP2891 ++ tristate "MPS MP2891" ++ help ++ If you say yes here you get hardware monitoring support for MPS ++ MP2891 Dual Loop Digital Multi-Phase Controller. ++ ++ This driver can also be built as a module. If so, the module will ++ be called mp2891. ++ + config SENSORS_MP2975 + tristate "MPS MP2975" + help +diff --git a/drivers/hwmon/pmbus/Makefile b/drivers/hwmon/pmbus/Makefile +index 0002dbe22d52..8e767d7b8c5b 100644 +--- a/drivers/hwmon/pmbus/Makefile ++++ b/drivers/hwmon/pmbus/Makefile +@@ -32,6 +32,7 @@ obj-$(CONFIG_SENSORS_MAX31785) += max31785.o + obj-$(CONFIG_SENSORS_MAX34440) += max34440.o + obj-$(CONFIG_SENSORS_MAX8688) += max8688.o + obj-$(CONFIG_SENSORS_MP2888) += mp2888.o ++obj-$(CONFIG_SENSORS_MP2891) += mp2891.o + obj-$(CONFIG_SENSORS_MP2975) += mp2975.o + obj-$(CONFIG_SENSORS_MP5023) += mp5023.o + obj-$(CONFIG_SENSORS_PLI1209BC) += pli1209bc.o +diff --git a/drivers/hwmon/pmbus/mp2891.c b/drivers/hwmon/pmbus/mp2891.c +new file mode 100644 +index 000000000000..e9e82844ee2a +--- /dev/null ++++ b/drivers/hwmon/pmbus/mp2891.c +@@ -0,0 +1,357 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later ++/* ++ * Hardware monitoring driver for MPS Multi-phase Digital VR Controllers(MP2891) ++ * ++ * Copyright (C) 2023 Nvidia ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include "pmbus.h" ++ ++/* Vendor specific registers. */ ++/* ++ * MP2891_MFR_SVI3_IOUT_PRT: ++ * bits 15:5 - reserved zeros; ++ * bits 4:3 - set SVI3 Vout digital filter ++ * b00: 5kHz ++ * b01: 2kHz ++ * b10: 1kHz ++ * b11: no filter ++ * bits 2:0 - define output current scaling selection of rail1. ++ * b000: 1 A/LSB ++ * b001: (1/32) A/LSB ++ * b010: (1/16) A/LSB ++ * b011: (1/8) A/LSB ++ * b100: (1/4) A/LSB ++ * b101: (1/2) A/LSB ++ * b110: 1 A/LSB ++ * b111: 2 A/LSB ++ */ ++#define MP2891_MFR_SVI3_IOUT_PRT 0x65 ++/* ++ * MP2891_MFR_VOUT_LOOP_CTRL: ++ * bits 15:14 define the VID step. ++ * b00: 6.25mV ++ * b01: 5mV ++ * b10: 2mV ++ * b11: 1mV ++ * bit 13 enable bit of 2.5mV resolution. ++ * b0: disable ++ * b1: enable ++ * bits 12:11 reserved zeros ++ * bit 10 defines rail remote sense amplifier gain: ++ * b0: 1 ++ * b1: 0.5 ++ * bit 9 DC reference_select ++ * b0: Comp EA uses Vfb and Vref ++ * b1: Comp EA uses Vdiff and Vref ++ * bit 8 enables DC loop calibration at DCM. ++ * b0: disable ++ * b1: enable ++ * bit 7 enables DC loop calibration both at DCM and CCM operation. ++ * b0: disable ++ * b1: enable ++ * bit 6 - holds DC loop when the PWM time interval meets PWM switching period condition ++ * set with PMBus command MFR_VR_CONFIG1 (B7h), bit [3:2]. ++ * b0: disable hold DC loop when PWM switching period condition meets ++ * b1: hold DC loop when PWM switching period condition meets ++ * bit 5 hold DC loop when phase count is changed. ++ * b0: disable hold DC loop when phase number change ++ * b1: hold the DC loop when phase number change. ++ * bit 4 hold DC loop regulation when a load transient event is detected. ++ * b0: disable hold DC loop when meets VFB+/- window condition ++ * b1: hold DC loop when meets VFB+/- window condition ++ * bits 3:0 set the DC loop minimal holding time in direct format. ++ */ ++#define MP2891_MFR_VOUT_LOOP_CTRL 0xbd ++ ++#define MP2891_VID_STEP_POS 14 ++#define MP2891_VID_STEP_MASK GENMASK(MP2891_VID_STEP_POS + 1, MP2891_VID_STEP_POS) ++#define MP2891_DAC_2P5MV_MASK BIT(13) ++#define MP2891_IOUT_SCALE_MASK GENMASK(2, 0) ++ ++#define MP2891_PAGE_NUM 2 ++#define MP2891_RAIL1_FUNC (PMBUS_HAVE_VIN | PMBUS_HAVE_VOUT | PMBUS_HAVE_IOUT | \ ++ PMBUS_HAVE_TEMP | PMBUS_HAVE_POUT | PMBUS_HAVE_PIN | \ ++ PMBUS_PHASE_VIRTUAL) ++ ++#define MP2891_RAIL2_FUNC (PMBUS_HAVE_VOUT | PMBUS_HAVE_IOUT | PMBUS_HAVE_TEMP | \ ++ PMBUS_HAVE_POUT | PMBUS_PHASE_VIRTUAL) ++ ++struct mp2891_data { ++ struct pmbus_driver_info info; ++ int vid_step[MP2891_PAGE_NUM]; ++ int iout_scale[MP2891_PAGE_NUM]; ++}; ++ ++#define to_mp2891_data(x) container_of(x, struct mp2891_data, info) ++ ++static int mp2891_read_vout(struct i2c_client *client, int page, int phase, int reg) ++{ ++ int ret; ++ ++ const struct pmbus_driver_info *info = pmbus_get_driver_info(client); ++ struct mp2891_data *data = to_mp2891_data(info); ++ ++ ret = pmbus_read_word_data(client, page, phase, reg); ++ ++ return ret < 0 ? ret : ret * data->vid_step[page] / 100; ++} ++ ++static int mp2891_read_iout(struct i2c_client *client, int page, int phase, int reg) ++{ ++ int ret; ++ ++ const struct pmbus_driver_info *info = pmbus_get_driver_info(client); ++ struct mp2891_data *data = to_mp2891_data(info); ++ ++ ret = pmbus_read_word_data(client, page, phase, reg); ++ ++ return ret < 0 ? ret : ret * data->iout_scale[page]; ++} ++ ++static int mp2891_read_byte_data(struct i2c_client *client, int page, int reg) ++{ ++ int ret; ++ ++ switch (reg) { ++ case PMBUS_VOUT_MODE: ++ /* ++ * Enforce VOUT direct format, since device allows to set the ++ * different formats for the different rails. Conversion from ++ * VID to direct provided by driver internally, in case it is ++ * necessary. ++ */ ++ ret = PB_VOUT_MODE_DIRECT; ++ break; ++ default: ++ ret = -EINVAL; ++ break; ++ } ++ ++ return ret; ++} ++ ++static int mp2891_read_word_data(struct i2c_client *client, int page, int phase, int reg) ++{ ++ switch (reg) { ++ case PMBUS_READ_VOUT: ++ return mp2891_read_vout(client, page, phase, reg); ++ case PMBUS_READ_IOUT: ++ return mp2891_read_iout(client, page, phase, reg); ++ case PMBUS_OT_WARN_LIMIT: ++ case PMBUS_OT_FAULT_LIMIT: ++ case PMBUS_UT_WARN_LIMIT: ++ case PMBUS_UT_FAULT_LIMIT: ++ case PMBUS_VOUT_OV_WARN_LIMIT: ++ case PMBUS_VIN_OV_WARN_LIMIT: ++ case PMBUS_POUT_MAX: ++ case PMBUS_POUT_OP_FAULT_LIMIT: ++ case PMBUS_MFR_VIN_MIN: ++ case PMBUS_MFR_VOUT_MIN: ++ case PMBUS_MFR_VIN_MAX: ++ case PMBUS_MFR_VOUT_MAX: ++ case PMBUS_MFR_IIN_MAX: ++ case PMBUS_MFR_IOUT_MAX: ++ case PMBUS_MFR_PIN_MAX: ++ case PMBUS_MFR_POUT_MAX: ++ case PMBUS_MFR_MAX_TEMP_1: ++ return -ENXIO; ++ default: ++ return -EINVAL; ++ } ++} ++ ++static int mp2891_identify_vid(struct i2c_client *client, struct mp2891_data *data, u32 reg, ++ int page) ++{ ++ int ret; ++ ++ ret = i2c_smbus_write_byte_data(client, PMBUS_PAGE, page); ++ if (ret < 0) ++ return ret; ++ ++ ret = i2c_smbus_read_word_data(client, reg); ++ if (ret < 0) ++ return ret; ++ ++ /* ++ * Obtain vid_step from MP2891_MFR_VOUT_LOOP_CTRL register: ++ * bit 13 = 1, the vid_step is below 2.5mV/LSB; ++ * bit 13 = 0, the vid_step is defined by bits 15:14: ++ * 00b - 6.25mV/LSB, 01b - 5mV/LSB, 10b - 2mV/LSB, 11b - 1mV ++ */ ++ if ((ret & MP2891_DAC_2P5MV_MASK) >> MP2891_VID_STEP_POS) { ++ data->vid_step[page] = 250; ++ return 0; ++ } ++ ++ switch ((ret & MP2891_VID_STEP_MASK) >> MP2891_VID_STEP_POS) { ++ case 0: ++ data->vid_step[page] = 625; ++ break; ++ case 1: ++ data->vid_step[page] = 500; ++ break; ++ case 2: ++ data->vid_step[page] = 200; ++ break; ++ default: ++ data->vid_step[page] = 100; ++ break; ++ } ++ ++ return 0; ++} ++ ++static int mp2891_identify_rails_vid(struct i2c_client *client, struct mp2891_data *data) ++{ ++ int ret; ++ ++ /* Identify vid_step for rail 1. */ ++ ret = mp2891_identify_vid(client, data, MP2891_MFR_VOUT_LOOP_CTRL, 0); ++ if (ret < 0) ++ return ret; ++ ++ /* Identify vid_step for rail 2. */ ++ return mp2891_identify_vid(client, data, MP2891_MFR_VOUT_LOOP_CTRL, 1); ++} ++ ++static int ++mp2891_iout_scale_get(struct i2c_client *client, struct mp2891_data *data, u32 reg, int page) ++{ ++ int ret; ++ ++ ret = i2c_smbus_write_byte_data(client, PMBUS_PAGE, page); ++ if (ret < 0) ++ return ret; ++ ++ ret = i2c_smbus_read_word_data(client, reg); ++ if (ret < 0) ++ return ret; ++ ++ /* ++ * Obtain iout_scale from the register MP2891_MFR_SVI3_IOUT_PRT, bits 2-0. ++ * The value is selected as below: ++ * 000b - 1A/LSB, 001b - (1/32)A/LSB, 010b - (1/16)A/LSB, ++ * 011b - (1/8)A/LSB, 100b - (1/4)A/LSB, 101b - (1/2)A/LSB ++ * 110b - 1A/LSB, 111b - 2A/LSB ++ */ ++ switch (ret & MP2891_IOUT_SCALE_MASK) { ++ case 0: ++ case 6: ++ data->iout_scale[page] = 32; ++ return 0; ++ case 1: ++ data->iout_scale[page] = 1; ++ return 0; ++ case 2: ++ data->iout_scale[page] = 2; ++ return 0; ++ case 3: ++ data->iout_scale[page] = 4; ++ return 0; ++ case 4: ++ data->iout_scale[page] = 8; ++ return 0; ++ case 5: ++ data->iout_scale[page] = 16; ++ return 0; ++ default: ++ data->iout_scale[page] = 64; ++ return 0; ++ } ++} ++ ++static int mp2891_rails_iout_scale_get(struct i2c_client *client, struct mp2891_data *data) ++{ ++ int ret; ++ ++ /* Get iout_scale for rail 1. */ ++ ret = mp2891_iout_scale_get(client, data, MP2891_MFR_SVI3_IOUT_PRT, 0); ++ /* Get iout_scale for rail 2. */ ++ return ret < 0 ? ret : mp2891_iout_scale_get(client, data, MP2891_MFR_SVI3_IOUT_PRT, 1); ++} ++ ++static struct pmbus_driver_info mp2891_info = { ++ .pages = MP2891_PAGE_NUM, ++ .format[PSC_VOLTAGE_IN] = direct, ++ .format[PSC_VOLTAGE_OUT] = direct, ++ .format[PSC_CURRENT_OUT] = direct, ++ .format[PSC_TEMPERATURE] = direct, ++ .format[PSC_POWER] = linear, ++ .m[PSC_VOLTAGE_IN] = 1, ++ .m[PSC_VOLTAGE_OUT] = 1, ++ .m[PSC_CURRENT_OUT] = 32, ++ .m[PSC_TEMPERATURE] = 1, ++ .R[PSC_VOLTAGE_IN] = 3, ++ .R[PSC_VOLTAGE_OUT] = 3, ++ .R[PSC_CURRENT_OUT] = 0, ++ .R[PSC_TEMPERATURE] = 0, ++ .b[PSC_VOLTAGE_IN] = 0, ++ .b[PSC_VOLTAGE_OUT] = 0, ++ .b[PSC_CURRENT_OUT] = 0, ++ .b[PSC_TEMPERATURE] = 0, ++ .func[0] = MP2891_RAIL1_FUNC, ++ .func[1] = MP2891_RAIL2_FUNC, ++ .read_word_data = mp2891_read_word_data, ++ .read_byte_data = mp2891_read_byte_data, ++}; ++ ++static int mp2891_probe(struct i2c_client *client) ++{ ++ struct pmbus_driver_info *info; ++ struct mp2891_data *data; ++ int ret; ++ ++ data = devm_kzalloc(&client->dev, sizeof(struct mp2891_data), GFP_KERNEL); ++ ++ if (!data) ++ return -ENOMEM; ++ ++ memcpy(&data->info, &mp2891_info, sizeof(*info)); ++ info = &data->info; ++ ++ /* Identify VID setting per rail - obtain the vid_step of output voltage. */ ++ ret = mp2891_identify_rails_vid(client, data); ++ if (ret < 0) ++ return ret; ++ ++ /* Get iout scale per rail - obtain current scale. */ ++ ret = mp2891_rails_iout_scale_get(client, data); ++ if (ret < 0) ++ return ret; ++ ++ return pmbus_do_probe(client, info); ++} ++ ++static const struct i2c_device_id mp2891_id[] = { ++ {"mp2891", 0}, ++ {} ++}; ++MODULE_DEVICE_TABLE(i2c, mp2891_id); ++ ++static const struct of_device_id __maybe_unused mp2891_of_match[] = { ++ {.compatible = "mps,mp2891"}, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, mp2891_of_match); ++ ++static struct i2c_driver mp2891_driver = { ++ .driver = { ++ .name = "mp2891", ++ .of_match_table = mp2891_of_match, ++ }, ++ .probe_new = mp2891_probe, ++ .id_table = mp2891_id, ++}; ++ ++module_i2c_driver(mp2891_driver); ++ ++MODULE_DESCRIPTION("PMBus driver for MPS MP2891 device"); ++MODULE_LICENSE("GPL"); ++MODULE_IMPORT_NS(PMBUS); +-- +2.20.1 + diff --git a/patch/0049-dt-bindings-trivial-devices-Add-mps-mp2891.patch b/patch/0049-dt-bindings-trivial-devices-Add-mps-mp2891.patch new file mode 100644 index 000000000000..9bf39cb2b022 --- /dev/null +++ b/patch/0049-dt-bindings-trivial-devices-Add-mps-mp2891.patch @@ -0,0 +1,30 @@ +From 98b6b44b7b190c664f41e482de4597571e700e7f Mon Sep 17 00:00:00 2001 +From: Vadim Pasternak +Date: Thu, 13 Jul 2023 06:20:05 +0000 +Subject: [PATCH backport 6.1.42 49/85] dt-bindings: trivial-devices: Add + mps,mp2891 + +Add new dual-loop, digital, multi-phase controller MP2891 fro +Monolithic Power Systems, Inc. (MPS) to trivial devices. + +Signed-off-by: Vadim Pasternak +--- + Documentation/devicetree/bindings/trivial-devices.yaml | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/Documentation/devicetree/bindings/trivial-devices.yaml b/Documentation/devicetree/bindings/trivial-devices.yaml +index 7637390dfe09..8e6c0bc60ee3 100644 +--- a/Documentation/devicetree/bindings/trivial-devices.yaml ++++ b/Documentation/devicetree/bindings/trivial-devices.yaml +@@ -113,6 +113,8 @@ properties: + - fsl,mpl3115 + # MPR121: Proximity Capacitive Touch Sensor Controller + - fsl,mpr121 ++ # Monolithic Power Systems Inc. multi-phase controller mp2891 ++ - mps,mp2891 + # Monolithic Power Systems Inc. multi-phase controller mp2888 + - mps,mp2888 + # Monolithic Power Systems Inc. multi-phase controller mp2975 +-- +2.20.1 + diff --git a/patch/0050-leds-mlxreg-Skip-setting-LED-color-during-initializa.patch b/patch/0050-leds-mlxreg-Skip-setting-LED-color-during-initializa.patch new file mode 100644 index 000000000000..3118617ea74c --- /dev/null +++ b/patch/0050-leds-mlxreg-Skip-setting-LED-color-during-initializa.patch @@ -0,0 +1,39 @@ +From 519742b99a6a2d6b8d5797d70608fdc954d2871a Mon Sep 17 00:00:00 2001 +From: Vadim Pasternak +Date: Wed, 7 Jul 2021 10:18:14 +0000 +Subject: [PATCH backport 6.1.42 55/85] leds: mlxreg: Skip setting LED color + during initialization + +Hardware controls LED through CPLD device and LED control ownership +passes to the software after it performs the first write operation for +any LED on a system. +For example, hardware sets "system" LED "green blink" during boot and +might change it to "red", in case something is went wrong from hardware +point of view. +The motivation for not setting LED during kernel initialization is for +keeping hardware settings visible for user, until user will not decide +to set LEDs according to user OS specific requirements. + +Signed-off-by: Vadim Pasternak +Reviewed-by: Michael Shych +--- + drivers/leds/leds-mlxreg.c | 3 --- + 1 file changed, 3 deletions(-) + +diff --git a/drivers/leds/leds-mlxreg.c b/drivers/leds/leds-mlxreg.c +index 215132f67c07..c0caf810b6d0 100644 +--- a/drivers/leds/leds-mlxreg.c ++++ b/drivers/leds/leds-mlxreg.c +@@ -246,9 +246,6 @@ static int mlxreg_led_config(struct mlxreg_led_priv_data *priv) + if (err) + return err; + +- if (led_cdev->brightness) +- mlxreg_led_brightness_set(led_cdev, +- led_cdev->brightness); + dev_info(led_cdev->dev, "label: %s, mask: 0x%02x, offset:0x%02x\n", + data->label, data->mask, data->reg); + } +-- +2.20.1 + diff --git a/patch/0053-platform-mellanox-Add-support-for-dynamic-I2C-channe.patch b/patch/0053-platform-mellanox-Add-support-for-dynamic-I2C-channe.patch new file mode 100644 index 000000000000..f396cf234c0b --- /dev/null +++ b/patch/0053-platform-mellanox-Add-support-for-dynamic-I2C-channe.patch @@ -0,0 +1,159 @@ +From 7831c5d10460c08cb5837827784677e0286d14e7 Mon Sep 17 00:00:00 2001 +From: Vadim Pasternak +Date: Sun, 30 Jul 2023 21:31:54 +0000 +Subject: [PATH backport v6.1 53/54] platform/mellanox: Add support for dynamic + I2C channels infrastructure + +Allow to support platform configuration for dynamically allocated I2C +channels. +Motivation is to support I2C channels allocated in a non-continuous +way. + +Currently hotplug platform driver data structure contains static mux +channels for I2C hotplug devices. These channels numbers can be updated +dynamically and returned by mux driver's callback through the adapters +array. +Thus, hotplug mux channels will be aligned according to the dynamic +adapters data. + +Signed-off-by: Vadim Pasternak +Reviewed-by: Michael Shych +--- + drivers/platform/x86/mlx-platform.c | 69 ++++++++++++++++++++++++----- + 1 file changed, 59 insertions(+), 10 deletions(-) + +diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c +index 44f107965832..9021597b5446 100644 +--- a/drivers/platform/x86/mlx-platform.c ++++ b/drivers/platform/x86/mlx-platform.c +@@ -15,6 +15,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -350,6 +351,7 @@ + * @hotplug_resources: system hotplug resources + * @hotplug_resources_size: size of system hotplug resources + * @hi2c_main_init_status: init status of I2C main bus ++ * @mux_added: number of added mux segments + * @irq_fpga: FPGA IRQ number + */ + struct mlxplat_priv { +@@ -364,6 +366,7 @@ struct mlxplat_priv { + struct resource *hotplug_resources; + unsigned int hotplug_resources_size; + u8 i2c_main_init_status; ++ int mux_added; + int irq_fpga; + }; + +@@ -453,7 +456,9 @@ static struct i2c_mux_reg_platform_data mlxplat_default_mux_data[] = { + /* Platform mux configuration variables */ + static int mlxplat_max_adap_num; + static int mlxplat_mux_num; ++static int mlxplat_mux_hotplug_num; + static struct i2c_mux_reg_platform_data *mlxplat_mux_data; ++static struct i2c_mux_regmap_platform_data *mlxplat_mux_regmap_data; + static struct notifier_block *mlxplat_reboot_nb; + + /* Platform extended mux data */ +@@ -6126,12 +6131,17 @@ static int mlxplat_mlxcpld_verify_bus_topology(int *nr) + /* Shift adapter ids, since expected parent adapter is not free. */ + *nr = i; + for (i = 0; i < mlxplat_mux_num; i++) { +- shift = *nr - mlxplat_mux_data[i].parent; +- mlxplat_mux_data[i].parent = *nr; +- mlxplat_mux_data[i].base_nr += shift; ++ if (mlxplat_mux_data) { ++ shift = *nr - mlxplat_mux_data[i].parent; ++ mlxplat_mux_data[i].parent = *nr; ++ mlxplat_mux_data[i].base_nr += shift; ++ } else if (mlxplat_mux_regmap_data) { ++ mlxplat_mux_regmap_data[i].parent = *nr; ++ } + } + +- if (shift > 0) ++ /* Shift bus only if mux provided by 'mlxplat_mux_data'. */ ++ if (shift > 0 && mlxplat_mux_data) + mlxplat_hotplug->shift_nr = shift; + + return 0; +@@ -6428,8 +6438,31 @@ mlxplat_i2c_mux_complition_notify(void *handle, struct i2c_adapter *parent, + struct i2c_adapter *adapters[]) + { + struct mlxplat_priv *priv = handle; ++ struct mlxreg_core_item *item; ++ int i, j; ++ ++ /* ++ * Hotplug platform driver data structure contains static mux channels for I2C hotplug ++ * devices. These channels numbers can be updated dynamically and returned by mux callback ++ * through the adapters array. Update mux channels according to the dynamic adapters data. ++ */ ++ if (priv->mux_added == mlxplat_mux_hotplug_num) { ++ item = mlxplat_hotplug->items; ++ for (i = 0; i < mlxplat_hotplug->counter; i++, item++) { ++ struct mlxreg_core_data *data = item->data; ++ ++ for (j = 0; j < item->count; j++, data++) { ++ if (data->hpdev.nr != MLXPLAT_CPLD_NR_NONE) ++ data->hpdev.nr = adapters[data->hpdev.nr - 2]->nr; ++ } ++ } ++ } + +- return mlxplat_post_init(priv); ++ /* Start post initialization only after last nux segment is added */ ++ if (++priv->mux_added == mlxplat_mux_num) ++ return mlxplat_post_init(priv); ++ ++ return 0; + } + + static int mlxplat_i2c_mux_topology_init(struct mlxplat_priv *priv) +@@ -6443,17 +6476,33 @@ static int mlxplat_i2c_mux_topology_init(struct mlxplat_priv *priv) + + priv->i2c_main_init_status = MLXPLAT_I2C_MAIN_BUS_HANDLE_CREATED; + for (i = 0; i < mlxplat_mux_num; i++) { +- priv->pdev_mux[i] = platform_device_register_resndata(&priv->pdev_i2c->dev, +- "i2c-mux-reg", i, NULL, 0, +- &mlxplat_mux_data[i], +- sizeof(mlxplat_mux_data[i])); ++ if (mlxplat_mux_data) { ++ priv->pdev_mux[i] = ++ platform_device_register_resndata(&priv->pdev_i2c->dev, ++ "i2c-mux-reg", i, NULL, 0, ++ &mlxplat_mux_data[i], ++ sizeof(mlxplat_mux_data[i])); ++ } else { ++ mlxplat_mux_regmap_data[i].handle = priv; ++ mlxplat_mux_regmap_data[i].regmap = priv->regmap; ++ mlxplat_mux_regmap_data[i].completion_notify = ++ mlxplat_i2c_mux_complition_notify; ++ priv->pdev_mux[i] = ++ platform_device_register_resndata(&priv->pdev_i2c->dev, ++ "i2c-mux-regmap", i, NULL, 0, ++ &mlxplat_mux_regmap_data[i], ++ sizeof(mlxplat_mux_regmap_data[i])); ++ } + if (IS_ERR(priv->pdev_mux[i])) { + err = PTR_ERR(priv->pdev_mux[i]); + goto fail_platform_mux_register; + } + } + +- return mlxplat_i2c_mux_complition_notify(priv, NULL, NULL); ++ if (mlxplat_mux_regmap_data && mlxplat_mux_regmap_data->completion_notify) ++ return 0; ++ ++ return mlxplat_post_init(priv); + + fail_platform_mux_register: + while (--i >= 0) +-- +2.20.1 + diff --git a/patch/0054-platform-mellanox-Introduce-support-for-switches-equ.patch b/patch/0054-platform-mellanox-Introduce-support-for-switches-equ.patch new file mode 100644 index 000000000000..f1c90d620363 --- /dev/null +++ b/patch/0054-platform-mellanox-Introduce-support-for-switches-equ.patch @@ -0,0 +1,312 @@ +From 3e4ff8f2195a3dc7b04bb5a1b9fd6b655f78a75e Mon Sep 17 00:00:00 2001 +From: Vadim Pasternak +Date: Mon, 24 Jul 2023 11:10:50 +0000 +Subject: [PATH backport v6.1 54/54] platform: mellanox: Introduce support for + switches equipped with new FPGA device + +Add support for Nvidia MQM97xx and MSN47xx family switches equipped with +new FPGA device. + +These switches are based on previous generation of MQM97xx and MSN47xx +switches, but COMe module uses new FPGA device. + +Platform configuration for new switches is based on the new VMOD0016 +class. Configuration is extended to support new register map with +callbacks supporting indirect addressing for PCIe-to-LPC bridge. +This bridge provides interface between FPGA at COMe board (directly +connected to CPU PCIe root complex) to CPLDs on switch board (which +cannot be connected directly to PCIe root complex). + +Signed-off-by: Vadim Pasternak +Reviewed-by: Michael Shych +--- + drivers/platform/x86/mlx-platform.c | 196 ++++++++++++++++++++++++++++ + 1 file changed, 196 insertions(+) + +diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c +index 9021597b5446..46958810e972 100644 +--- a/drivers/platform/x86/mlx-platform.c ++++ b/drivers/platform/x86/mlx-platform.c +@@ -183,6 +183,9 @@ + #define MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET 0xfb + #define MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET 0xfc + #define MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET 0xfd ++#define MLXPLAT_CPLD_LPC_REG_EXT_MIN_OFFSET 0x100 ++#define MLXPLAT_CPLD_LPC_REG_EXT_MID_OFFSET 0x195 ++#define MLXPLAT_CPLD_LPC_REG_EXT_MAX_OFFSET 0x1ff + #define MLXPLAT_CPLD_LPC_IO_RANGE 0x100 + + #define MLXPLAT_CPLD_LPC_PIO_OFFSET 0x10000UL +@@ -277,6 +280,7 @@ + /* Maximum number of possible physical buses equipped on system */ + #define MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM 16 + #define MLXPLAT_CPLD_MAX_PHYS_EXT_ADAPTER_NUM 24 ++#define MLXPLAT_CPLD_DEFAULT_MUX_HOTPLUG_VECTOR 0 + + /* Number of channels in group */ + #define MLXPLAT_CPLD_GRP_CHNL_NUM 8 +@@ -338,6 +342,21 @@ + #define PCI_DEVICE_ID_LATTICE_I2C_BRIDGE 0x9c2f + #define PCI_DEVICE_ID_LATTICE_JTAG_BRIDGE 0x9c30 + #define PCI_DEVICE_ID_LATTICE_LPC_BRIDGE 0x9c32 ++#define MLXPLAT_FPGA_PCI_BAR0_SIZE 0x4000 ++#define MLXPLAT_FPGA_PCI_BASE_OFFSET 0x00000000 ++#define MLXPLAT_FPGA_PCI_MSB_ADDR 0x25 ++#define MLXPLAT_FPGA_PCI_MSB_EXT_ADDR 0x20 ++#define MLXPLAT_FPGA_PCI_LSB_ADDR_OFFSET MLXPLAT_FPGA_PCI_BASE_OFFSET ++#define MLXPLAT_FPGA_PCI_MSB_ADDR_OFFSET (MLXPLAT_FPGA_PCI_BASE_OFFSET + 0x01) ++#define MLXPLAT_FPGA_PCI_DATA_OUT_OFFSET (MLXPLAT_FPGA_PCI_BASE_OFFSET + 0x02) ++#define MLXPLAT_FPGA_PCI_DATA_IN_OFFSET (MLXPLAT_FPGA_PCI_BASE_OFFSET + 0x03) ++#define MLXPLAT_FPGA_PCI_CTRL_OFFSET (MLXPLAT_FPGA_PCI_BASE_OFFSET + 0x04) ++#define MLXPLAT_FPGA_PCI_STAT_OFFSET (MLXPLAT_FPGA_PCI_BASE_OFFSET + 0x05) ++ ++#define MLXPLAT_FPGA_PCI_CTRL_READ BIT(0) ++#define MLXPLAT_FPGA_PCI_CTRL_WRITE BIT(1) ++#define MLXPLAT_FPGA_PCI_COMPLETED GENMASK(1, 0) ++#define MLXPLAT_FPGA_PCI_TO 50 /* usec */ + + /* mlxplat_priv - platform private data + * @pdev_i2c - i2c controller platform device +@@ -453,6 +472,28 @@ static struct i2c_mux_reg_platform_data mlxplat_default_mux_data[] = { + + }; + ++/* Default channels vector for regmap mux. */ ++static int mlxplat_default_regmap_mux_chan[] = { 1, 2, 3, 4, 5, 6, 7, 8 }; ++ ++/* Platform regmap mux data */ ++static struct i2c_mux_regmap_platform_data mlxplat_default_regmap_mux_data[] = { ++ { ++ .parent = 1, ++ .chan_ids = mlxplat_default_regmap_mux_chan, ++ .num_adaps = ARRAY_SIZE(mlxplat_default_regmap_mux_chan), ++ .sel_reg_addr = MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET, ++ .reg_size = 1, ++ }, ++ { ++ .parent = 1, ++ .chan_ids = mlxplat_default_regmap_mux_chan, ++ .num_adaps = ARRAY_SIZE(mlxplat_default_regmap_mux_chan), ++ .sel_reg_addr = MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET, ++ .reg_size = 1, ++ }, ++ ++}; ++ + /* Platform mux configuration variables */ + static int mlxplat_max_adap_num; + static int mlxplat_mux_num; +@@ -3540,6 +3581,12 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { + .mask = GENMASK(7, 0) & ~BIT(2), + .mode = 0200, + }, ++ { ++ .label = "kexec_activated", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), ++ .mode = 0644, ++ }, + { + .label = "erot1_reset", + .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET, +@@ -5065,6 +5112,7 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) + case MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_EXT_MIN_OFFSET ... MLXPLAT_CPLD_LPC_REG_EXT_MAX_OFFSET: + return true; + } + return false; +@@ -5230,6 +5278,7 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) + case MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET: + case MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET: + case MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_EXT_MIN_OFFSET ... MLXPLAT_CPLD_LPC_REG_EXT_MAX_OFFSET: + return true; + } + return false; +@@ -5387,6 +5436,7 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) + case MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET: + case MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET: + case MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_EXT_MIN_OFFSET ... MLXPLAT_CPLD_LPC_REG_EXT_MAX_OFFSET: + return true; + } + return false; +@@ -5417,6 +5467,14 @@ static const struct reg_default mlxplat_mlxcpld_regmap_ng400[] = { + { MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 0x00 }, + }; + ++static const struct reg_default mlxplat_mlxcpld_regmap_bf3[] = { ++ { MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, 0xc1 }, ++ { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 }, ++ { MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET, 0x00 }, ++ { MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 0x00 }, ++ { MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 0x00 }, ++}; ++ + static const struct reg_default mlxplat_mlxcpld_regmap_rack_switch[] = { + { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, MLXPLAT_REGMAP_NVSWITCH_PWM_DEFAULT }, + { MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET, 0x00 }, +@@ -5545,6 +5603,114 @@ static const struct regmap_config mlxplat_mlxcpld_regmap_config_eth_modular = { + .reg_write = mlxplat_mlxcpld_reg_write, + }; + ++/* Wait completion routine for indirect access for register map */ ++static int mlxplat_fpga_completion_wait(struct mlxplat_mlxcpld_regmap_context *ctx) ++{ ++ unsigned long end; ++ u8 status; ++ ++ end = jiffies + msecs_to_jiffies(MLXPLAT_FPGA_PCI_TO); ++ do { ++ status = ioread8(ctx->base + MLXPLAT_FPGA_PCI_STAT_OFFSET); ++ if (!(status & MLXPLAT_FPGA_PCI_COMPLETED)) ++ return 0; ++ cond_resched(); ++ } while (time_before(jiffies, end)); ++ ++ return -EIO; ++} ++ ++/* Read callback for indirect register map access */ ++static int mlxplat_fpga_reg_read(void *context, unsigned int reg, unsigned int *val) ++{ ++ struct mlxplat_mlxcpld_regmap_context *ctx = context; ++ unsigned int msb_off = MLXPLAT_FPGA_PCI_MSB_ADDR; ++ int err; ++ ++ if (reg >= MLXPLAT_CPLD_LPC_REG_EXT_MIN_OFFSET) { ++ if (reg <= MLXPLAT_CPLD_LPC_REG_EXT_MID_OFFSET) { ++ /* Access to 2-nd FPGA bank */ ++ *val = ioread8(i2c_bridge_addr + reg - ++ MLXPLAT_CPLD_LPC_REG_EXT_MIN_OFFSET); ++ return 0; ++ } ++ /* Access to 3-rd FPGA bank */ ++ reg -= MLXPLAT_CPLD_LPC_REG_EXT_MIN_OFFSET; ++ msb_off = MLXPLAT_FPGA_PCI_MSB_EXT_ADDR; ++ } ++ ++ /* Verify there is no pending transactions */ ++ err = mlxplat_fpga_completion_wait(ctx); ++ if (err) ++ return err; ++ ++ /* Set address in register space */ ++ iowrite8(msb_off, ctx->base + MLXPLAT_FPGA_PCI_MSB_ADDR_OFFSET); ++ iowrite8(reg, ctx->base + MLXPLAT_FPGA_PCI_LSB_ADDR_OFFSET); ++ /* Activate read operation */ ++ iowrite8(MLXPLAT_FPGA_PCI_CTRL_READ, ctx->base + MLXPLAT_FPGA_PCI_CTRL_OFFSET); ++ /* Verify transaction completion */ ++ err = mlxplat_fpga_completion_wait(ctx); ++ if (err) ++ return err; ++ ++ /* Read data */ ++ *val = ioread8(ctx->base + MLXPLAT_FPGA_PCI_DATA_IN_OFFSET); ++ ++ return 0; ++} ++ ++/* Write callback for indirect register map access */ ++static int mlxplat_fpga_reg_write(void *context, unsigned int reg, unsigned int val) ++{ ++ struct mlxplat_mlxcpld_regmap_context *ctx = context; ++ unsigned int msb_off = MLXPLAT_FPGA_PCI_MSB_ADDR; ++ int err; ++ ++ if (reg >= MLXPLAT_CPLD_LPC_REG_EXT_MIN_OFFSET) { ++ if (reg <= MLXPLAT_CPLD_LPC_REG_EXT_MID_OFFSET) { ++ /* Access to 2-nd FPGA bank */ ++ iowrite8(val, i2c_bridge_addr + reg - MLXPLAT_CPLD_LPC_REG_EXT_MIN_OFFSET); ++ /* Flush modification */ ++ wmb(); ++ return 0; ++ } ++ ++ /* Access to 3-rd FPGA bank */ ++ reg -= MLXPLAT_CPLD_LPC_REG_EXT_MIN_OFFSET; ++ msb_off = MLXPLAT_FPGA_PCI_MSB_EXT_ADDR; ++ } ++ ++ /* Verify there is no pending transactions */ ++ err = mlxplat_fpga_completion_wait(ctx); ++ if (err) ++ return err; ++ ++ /* Set address in register space */ ++ iowrite8(msb_off, ctx->base + MLXPLAT_FPGA_PCI_MSB_ADDR_OFFSET); ++ iowrite8(reg, ctx->base + MLXPLAT_FPGA_PCI_LSB_ADDR_OFFSET); ++ /* Set data to be written */ ++ iowrite8(val, ctx->base + MLXPLAT_FPGA_PCI_DATA_OUT_OFFSET); ++ /* Activate write operation */ ++ iowrite8(MLXPLAT_FPGA_PCI_CTRL_WRITE, ctx->base + MLXPLAT_FPGA_PCI_CTRL_OFFSET); ++ ++ return mlxplat_fpga_completion_wait(ctx); ++} ++ ++static const struct regmap_config mlxplat_fpga_regmap_config_bf3_comex_default = { ++ .reg_bits = 9, ++ .val_bits = 8, ++ .max_register = 511, ++ .cache_type = REGCACHE_FLAT, ++ .writeable_reg = mlxplat_mlxcpld_writeable_reg, ++ .readable_reg = mlxplat_mlxcpld_readable_reg, ++ .volatile_reg = mlxplat_mlxcpld_volatile_reg, ++ .reg_defaults = mlxplat_mlxcpld_regmap_bf3, ++ .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_bf3), ++ .reg_read = mlxplat_fpga_reg_read, ++ .reg_write = mlxplat_fpga_reg_write, ++}; ++ + static struct resource mlxplat_mlxcpld_resources[] = { + [0] = DEFINE_RES_IRQ_NAMED(MLXPLAT_CPLD_LPC_SYSIRQ, "mlxreg-hotplug"), + }; +@@ -5927,6 +6093,30 @@ static int __init mlxplat_dmi_l1_switch_matched(const struct dmi_system_id *dmi) + return mlxplat_register_platform_device(); + } + ++static int __init mlxplat_dmi_bf3_comex_default_matched(const struct dmi_system_id *dmi) ++{ ++ int i; ++ ++ mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; ++ mlxplat_mux_hotplug_num = MLXPLAT_CPLD_DEFAULT_MUX_HOTPLUG_VECTOR; ++ mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_regmap_mux_data); ++ mlxplat_mux_regmap_data = mlxplat_default_regmap_mux_data; ++ mlxplat_hotplug = &mlxplat_mlxcpld_ext_data; ++ mlxplat_hotplug->deferred_nr = ++ mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; ++ mlxplat_led = &mlxplat_default_ng_led_data; ++ mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; ++ mlxplat_fan = &mlxplat_default_fan_data; ++ for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) ++ mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; ++ mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; ++ mlxplat_regmap_config = &mlxplat_fpga_regmap_config_bf3_comex_default; ++ mlxplat_reboot_nb = &mlxplat_reboot_default_nb; ++ pm_power_off = mlxplat_poweroff; ++ ++ return 1; ++} ++ + static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { + { + .callback = mlxplat_dmi_default_wc_matched, +@@ -6015,6 +6205,12 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { + DMI_MATCH(DMI_BOARD_NAME, "VMOD0015"), + }, + }, ++ { ++ .callback = mlxplat_dmi_bf3_comex_default_matched, ++ .matches = { ++ DMI_MATCH(DMI_BOARD_NAME, "VMOD0016"), ++ }, ++ }, + { + .callback = mlxplat_dmi_l1_switch_matched, + .matches = { +-- +2.20.1 + diff --git a/patch/0055-mellanox-Relocate-mlx-platform-driver.patch b/patch/0055-mellanox-Relocate-mlx-platform-driver.patch new file mode 100644 index 000000000000..3b5f6b9400fe --- /dev/null +++ b/patch/0055-mellanox-Relocate-mlx-platform-driver.patch @@ -0,0 +1,98 @@ +From a4eca7c60f361575fb15bcab6fdcd39c795c8244 Mon Sep 17 00:00:00 2001 +From: Vadim Pasternak +Date: Mon, 24 Jul 2023 11:52:56 +0000 +Subject: [PATCH backport 6.1.42 58/85] mellanox: Relocate mlx-platform driver + +Move 'mlx-platform' driver 'x86' to 'mellanox' folder. + +Motivation to allow running it on systems with ARM architecture. + +Signed-off-by: Vadim Pasternak +Reviewed-by: Michael Shych +--- + drivers/platform/mellanox/Kconfig | 12 ++++++++++++ + drivers/platform/mellanox/Makefile | 1 + + drivers/platform/{x86 => mellanox}/mlx-platform.c | 0 + drivers/platform/x86/Kconfig | 13 ------------- + drivers/platform/x86/Makefile | 1 - + 5 files changed, 13 insertions(+), 14 deletions(-) + rename drivers/platform/{x86 => mellanox}/mlx-platform.c (100%) + +diff --git a/drivers/platform/mellanox/Kconfig b/drivers/platform/mellanox/Kconfig +index 382793e73a60..70b628834b4f 100644 +--- a/drivers/platform/mellanox/Kconfig ++++ b/drivers/platform/mellanox/Kconfig +@@ -14,6 +14,18 @@ menuconfig MELLANOX_PLATFORM + + if MELLANOX_PLATFORM + ++config MLX_PLATFORM ++ tristate "Mellanox Technologies platform support" ++ depends on I2C && REGMAP ++ help ++ This option enables system support for the Mellanox Technologies ++ platform. The Mellanox systems provide data center networking ++ solutions based on Virtual Protocol Interconnect (VPI) technology ++ enable seamless connectivity to 56/100Gb/s InfiniBand or 10/40/56GbE ++ connection. ++ ++ If you have a Mellanox system, say Y or M here. ++ + config MLXREG_HOTPLUG + tristate "Mellanox platform hotplug driver support" + depends on HWMON +diff --git a/drivers/platform/mellanox/Makefile b/drivers/platform/mellanox/Makefile +index 04703c0416b1..ba56485cbe8c 100644 +--- a/drivers/platform/mellanox/Makefile ++++ b/drivers/platform/mellanox/Makefile +@@ -3,6 +3,7 @@ + # Makefile for linux/drivers/platform/mellanox + # Mellanox Platform-Specific Drivers + # ++obj-$(CONFIG_MLX_PLATFORM) += mlx-platform.o + obj-$(CONFIG_MLXBF_BOOTCTL) += mlxbf-bootctl.o + obj-$(CONFIG_MLXBF_PMC) += mlxbf-pmc.o + obj-$(CONFIG_MLXBF_TMFIFO) += mlxbf-tmfifo.o +diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c +similarity index 100% +rename from drivers/platform/x86/mlx-platform.c +rename to drivers/platform/mellanox/mlx-platform.c +diff --git a/drivers/platform/x86/Kconfig b/drivers/platform/x86/Kconfig +index 1396a839dd8a..f11136bbf88d 100644 +--- a/drivers/platform/x86/Kconfig ++++ b/drivers/platform/x86/Kconfig +@@ -954,19 +954,6 @@ config SERIAL_MULTI_INSTANTIATE + To compile this driver as a module, choose M here: the module + will be called serial-multi-instantiate. + +-config MLX_PLATFORM +- tristate "Mellanox Technologies platform support" +- depends on I2C +- select REGMAP +- help +- This option enables system support for the Mellanox Technologies +- platform. The Mellanox systems provide data center networking +- solutions based on Virtual Protocol Interconnect (VPI) technology +- enable seamless connectivity to 56/100Gb/s InfiniBand or 10/40/56GbE +- connection. +- +- If you have a Mellanox system, say Y or M here. +- + config TOUCHSCREEN_DMI + bool "DMI based touchscreen configuration info" + depends on ACPI && DMI && I2C=y && TOUCHSCREEN_SILEAD +diff --git a/drivers/platform/x86/Makefile b/drivers/platform/x86/Makefile +index 1d3d1b02541b..aee1bc4b0a80 100644 +--- a/drivers/platform/x86/Makefile ++++ b/drivers/platform/x86/Makefile +@@ -109,7 +109,6 @@ obj-$(CONFIG_TOPSTAR_LAPTOP) += topstar-laptop.o + # Platform drivers + obj-$(CONFIG_FW_ATTR_CLASS) += firmware_attributes_class.o + obj-$(CONFIG_SERIAL_MULTI_INSTANTIATE) += serial-multi-instantiate.o +-obj-$(CONFIG_MLX_PLATFORM) += mlx-platform.o + obj-$(CONFIG_TOUCHSCREEN_DMI) += touchscreen_dmi.o + obj-$(CONFIG_WIRELESS_HOTKEY) += wireless-hotkey.o + obj-$(CONFIG_X86_ANDROID_TABLETS) += x86-android-tablets.o +-- +2.20.1 + diff --git a/patch/0057-Documentation-ABI-Add-new-attribute-for-mlxreg-io-sy.patch b/patch/0057-Documentation-ABI-Add-new-attribute-for-mlxreg-io-sy.patch deleted file mode 100644 index 943780109efd..000000000000 --- a/patch/0057-Documentation-ABI-Add-new-attribute-for-mlxreg-io-sy.patch +++ /dev/null @@ -1,74 +0,0 @@ -From fe6caa3afd2525ee83f1b2ee13a1650c596f9e1c Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Sun, 13 Aug 2023 17:51:39 +0000 -Subject: [PATH backport v6.1 32/32] Documentation/ABI: Add new attribute for - mlxreg-io sysfs interfaces - -Link: https://www.spinics.net/lists/platform-driver-x86/msg39648.html - -Add documentation for the new attributes: -- CPLD versioning: "cpld5_pn", "cpld5_version", "cpld5_version_min". -- JTAG capability: "jtag_cap", indicating the available method of - CPLD/FPGA devices field update. -- System lid status: "lid_open". -- Reset caused by long press of power button: "reset_long_pwr_pb". - -Signed-off-by: Vadim Pasternak -Reviewed-by: Michael Shych ---- - .../ABI/stable/sysfs-driver-mlxreg-io | 42 +++++++++++++++++++ - 1 file changed, 42 insertions(+) - -diff --git a/Documentation/ABI/stable/sysfs-driver-mlxreg-io b/Documentation/ABI/stable/sysfs-driver-mlxreg-io -index 60953903d007..633be2bf2cd0 100644 ---- a/Documentation/ABI/stable/sysfs-driver-mlxreg-io -+++ b/Documentation/ABI/stable/sysfs-driver-mlxreg-io -@@ -662,3 +662,45 @@ Description: This file shows the system reset cause due to AC power failure. - Value 1 in file means this is reset cause, 0 - otherwise. - - The file is read only. -+ -+What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld5_pn -+What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld5_version -+What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld5_version_min -+Date: August 2023 -+KernelVersion: 6.6 -+Contact: Vadim Pasternak -+Description: These files show with which CPLD part numbers, version and minor -+ versions have been burned the 5-th CPLD device equipped on a -+ system. -+ -+ The files are read only. -+ -+What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/jtag_cap -+Date: August 2023 -+KernelVersion: 6.6 -+Contact: Vadim Pasternak -+Description: This file indicates the available method of CPLD/FPGA devices -+ field update through the JTAG chain: -+ b00 - field update through LPC bus register memory space. -+ b01 - Reserved. -+ b10 - Reserved. -+ b11 - field update through CPU GPIOs bit-banging. -+ -+ The file is read only. -+ -+What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/lid_open -+Date: August 2023 -+KernelVersion: 6.6 -+Contact: Vadim Pasternak -+Description: 1 - indicates that system lid is opened, otherwise 0. -+ -+ The file is read only. -+ -+What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_long_pwr_pb -+Date: August 2023 -+KernelVersion: 6.6 -+Contact: Vadim Pasternak -+Description: This file if set 1 indicates that system has been reset by -+ long press of power button. -+ -+ The file is read only. --- -2.20.1 - diff --git a/patch/0061-pinctrl-Introduce-struct-pinfunction-and-PINCTRL_PIN.patch b/patch/0061-pinctrl-Introduce-struct-pinfunction-and-PINCTRL_PIN.patch deleted file mode 100644 index ee2b41fb18de..000000000000 --- a/patch/0061-pinctrl-Introduce-struct-pinfunction-and-PINCTRL_PIN.patch +++ /dev/null @@ -1,59 +0,0 @@ -From aa410417368e3141e96e5331c1353b0e9dcf60fa Mon Sep 17 00:00:00 2001 -From: Andy Shevchenko -Date: Mon, 19 Dec 2022 14:42:33 +0200 -Subject: [PATCH backport 6.1.42 61/85] pinctrl: Introduce struct pinfunction - and PINCTRL_PINFUNCTION() macro - -BugLink: https://bugs.launchpad.net/bugs/2012743 - -There are many pin control drivers define their own data type for -pin function representation which is the same or embed the same data -as newly introduced one. Provide the data type and convenient macro -for all pin control drivers. - -Signed-off-by: Andy Shevchenko -Reviewed-by: Linus Walleij -Acked-by: Mika Westerberg -(cherry picked from commit 443a0a0f0cf4f432c7af6654b7f2f920d411d379) -Signed-off-by: Asmaa Mnebhi -Acked-by: Tim Gardner -Acked-by: Bartlomiej Zolnierkiewicz -Signed-off-by: Bartlomiej Zolnierkiewicz ---- - include/linux/pinctrl/pinctrl.h | 20 ++++++++++++++++++++ - 1 file changed, 20 insertions(+) - -diff --git a/include/linux/pinctrl/pinctrl.h b/include/linux/pinctrl/pinctrl.h -index 487117ccb1bc..fb25085d0922 100644 ---- a/include/linux/pinctrl/pinctrl.h -+++ b/include/linux/pinctrl/pinctrl.h -@@ -206,6 +206,26 @@ extern int pinctrl_get_group_pins(struct pinctrl_dev *pctldev, - const char *pin_group, const unsigned **pins, - unsigned *num_pins); - -+/** -+ * struct pinfunction - Description about a function -+ * @name: Name of the function -+ * @groups: An array of groups for this function -+ * @ngroups: Number of groups in @groups -+ */ -+struct pinfunction { -+ const char *name; -+ const char * const *groups; -+ size_t ngroups; -+}; -+ -+/* Convenience macro to define a single named pinfunction */ -+#define PINCTRL_PINFUNCTION(_name, _groups, _ngroups) \ -+(struct pinfunction) { \ -+ .name = (_name), \ -+ .groups = (_groups), \ -+ .ngroups = (_ngroups), \ -+ } -+ - #if IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_PINCTRL) - extern struct pinctrl_dev *of_pinctrl_get(struct device_node *np); - #else --- -2.20.1 - diff --git a/patch/0062-pinctrl-mlxbf3-Add-pinctrl-driver-support.patch b/patch/0062-pinctrl-mlxbf3-Add-pinctrl-driver-support.patch deleted file mode 100644 index 4836bc49aa14..000000000000 --- a/patch/0062-pinctrl-mlxbf3-Add-pinctrl-driver-support.patch +++ /dev/null @@ -1,393 +0,0 @@ -From 1f79825ac209a5aac6e13c87903a6506a5b78565 Mon Sep 17 00:00:00 2001 -From: Asmaa Mnebhi -Date: Wed, 15 Mar 2023 17:50:27 -0400 -Subject: [PATCH backport 6.1.42 62/85] pinctrl: mlxbf3: Add pinctrl driver - support - -BugLink: https://bugs.launchpad.net/bugs/2012743 - -NVIDIA BlueField-3 SoC has a few pins that can be used as GPIOs -or take the default hardware functionality. Add a driver for -the pin muxing. - -Signed-off-by: Asmaa Mnebhi -Reviewed-by: Andy Shevchenko -Link: https://lore.kernel.org/r/20230315215027.30685-3-asmaa@nvidia.com -Signed-off-by: Linus Walleij -(cherry picked from commit d11f932808dc689717e409bbc81b5093e7902fc9 linux-next) -Signed-off-by: Asmaa Mnebhi -Acked-by: Tim Gardner -Acked-by: Bartlomiej Zolnierkiewicz -Signed-off-by: Bartlomiej Zolnierkiewicz ---- - drivers/pinctrl/Kconfig | 13 ++ - drivers/pinctrl/Makefile | 1 + - drivers/pinctrl/pinctrl-mlxbf3.c | 320 +++++++++++++++++++++++++++++++ - 3 files changed, 334 insertions(+) - create mode 100644 drivers/pinctrl/pinctrl-mlxbf3.c - -diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig -index f71fefff400f..92e97d5bf91f 100644 ---- a/drivers/pinctrl/Kconfig -+++ b/drivers/pinctrl/Kconfig -@@ -512,6 +512,19 @@ config PINCTRL_ZYNQMP - This driver can also be built as a module. If so, the module - will be called pinctrl-zynqmp. - -+config PINCTRL_MLXBF3 -+ tristate "NVIDIA BlueField-3 SoC Pinctrl driver" -+ depends on (MELLANOX_PLATFORM && ARM64) || COMPILE_TEST -+ select PINMUX -+ select GPIOLIB -+ select GPIOLIB_IRQCHIP -+ select GPIO_MLXBF3 -+ help -+ Say Y to select the pinctrl driver for BlueField-3 SoCs. -+ This pin controller allows selecting the mux function for -+ each pin. This driver can also be built as a module called -+ pinctrl-mlxbf3. -+ - source "drivers/pinctrl/actions/Kconfig" - source "drivers/pinctrl/aspeed/Kconfig" - source "drivers/pinctrl/bcm/Kconfig" -diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile -index 89bfa01b5231..89fda1b780b7 100644 ---- a/drivers/pinctrl/Makefile -+++ b/drivers/pinctrl/Makefile -@@ -36,6 +36,7 @@ obj-$(CONFIG_PINCTRL_MCP23S08_SPI) += pinctrl-mcp23s08_spi.o - obj-$(CONFIG_PINCTRL_MCP23S08) += pinctrl-mcp23s08.o - obj-$(CONFIG_PINCTRL_MICROCHIP_SGPIO) += pinctrl-microchip-sgpio.o - obj-$(CONFIG_PINCTRL_OCELOT) += pinctrl-ocelot.o -+obj-$(CONFIG_PINCTRL_MLXBF3) += pinctrl-mlxbf3.o - obj-$(CONFIG_PINCTRL_OXNAS) += pinctrl-oxnas.o - obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o - obj-$(CONFIG_PINCTRL_PIC32) += pinctrl-pic32.o -diff --git a/drivers/pinctrl/pinctrl-mlxbf3.c b/drivers/pinctrl/pinctrl-mlxbf3.c -new file mode 100644 -index 000000000000..3698f7bbd88d ---- /dev/null -+++ b/drivers/pinctrl/pinctrl-mlxbf3.c -@@ -0,0 +1,320 @@ -+// SPDX-License-Identifier: GPL-2.0-only or BSD-3-Clause -+/* Copyright (C) 2022 NVIDIA CORPORATION & AFFILIATES */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#define MLXBF3_NGPIOS_GPIO0 32 -+#define MLXBF3_MAX_GPIO_PINS 56 -+ -+enum { -+ MLXBF3_GPIO_HW_MODE, -+ MLXBF3_GPIO_SW_MODE, -+}; -+ -+struct mlxbf3_pinctrl { -+ void __iomem *fw_ctrl_set0; -+ void __iomem *fw_ctrl_clr0; -+ void __iomem *fw_ctrl_set1; -+ void __iomem *fw_ctrl_clr1; -+ struct device *dev; -+ struct pinctrl_dev *pctl; -+ struct pinctrl_gpio_range gpio_range; -+}; -+ -+#define MLXBF3_GPIO_RANGE(_id, _pinbase, _gpiobase, _npins) \ -+ { \ -+ .name = "mlxbf3_gpio_range", \ -+ .id = _id, \ -+ .base = _gpiobase, \ -+ .pin_base = _pinbase, \ -+ .npins = _npins, \ -+ } -+ -+static struct pinctrl_gpio_range mlxbf3_pinctrl_gpio_ranges[] = { -+ MLXBF3_GPIO_RANGE(0, 0, 480, 32), -+ MLXBF3_GPIO_RANGE(1, 32, 456, 24), -+}; -+ -+static const struct pinctrl_pin_desc mlxbf3_pins[] = { -+ PINCTRL_PIN(0, "gpio0"), -+ PINCTRL_PIN(1, "gpio1"), -+ PINCTRL_PIN(2, "gpio2"), -+ PINCTRL_PIN(3, "gpio3"), -+ PINCTRL_PIN(4, "gpio4"), -+ PINCTRL_PIN(5, "gpio5"), -+ PINCTRL_PIN(6, "gpio6"), -+ PINCTRL_PIN(7, "gpio7"), -+ PINCTRL_PIN(8, "gpio8"), -+ PINCTRL_PIN(9, "gpio9"), -+ PINCTRL_PIN(10, "gpio10"), -+ PINCTRL_PIN(11, "gpio11"), -+ PINCTRL_PIN(12, "gpio12"), -+ PINCTRL_PIN(13, "gpio13"), -+ PINCTRL_PIN(14, "gpio14"), -+ PINCTRL_PIN(15, "gpio15"), -+ PINCTRL_PIN(16, "gpio16"), -+ PINCTRL_PIN(17, "gpio17"), -+ PINCTRL_PIN(18, "gpio18"), -+ PINCTRL_PIN(19, "gpio19"), -+ PINCTRL_PIN(20, "gpio20"), -+ PINCTRL_PIN(21, "gpio21"), -+ PINCTRL_PIN(22, "gpio22"), -+ PINCTRL_PIN(23, "gpio23"), -+ PINCTRL_PIN(24, "gpio24"), -+ PINCTRL_PIN(25, "gpio25"), -+ PINCTRL_PIN(26, "gpio26"), -+ PINCTRL_PIN(27, "gpio27"), -+ PINCTRL_PIN(28, "gpio28"), -+ PINCTRL_PIN(29, "gpio29"), -+ PINCTRL_PIN(30, "gpio30"), -+ PINCTRL_PIN(31, "gpio31"), -+ PINCTRL_PIN(32, "gpio32"), -+ PINCTRL_PIN(33, "gpio33"), -+ PINCTRL_PIN(34, "gpio34"), -+ PINCTRL_PIN(35, "gpio35"), -+ PINCTRL_PIN(36, "gpio36"), -+ PINCTRL_PIN(37, "gpio37"), -+ PINCTRL_PIN(38, "gpio38"), -+ PINCTRL_PIN(39, "gpio39"), -+ PINCTRL_PIN(40, "gpio40"), -+ PINCTRL_PIN(41, "gpio41"), -+ PINCTRL_PIN(42, "gpio42"), -+ PINCTRL_PIN(43, "gpio43"), -+ PINCTRL_PIN(44, "gpio44"), -+ PINCTRL_PIN(45, "gpio45"), -+ PINCTRL_PIN(46, "gpio46"), -+ PINCTRL_PIN(47, "gpio47"), -+ PINCTRL_PIN(48, "gpio48"), -+ PINCTRL_PIN(49, "gpio49"), -+ PINCTRL_PIN(50, "gpio50"), -+ PINCTRL_PIN(51, "gpio51"), -+ PINCTRL_PIN(52, "gpio52"), -+ PINCTRL_PIN(53, "gpio53"), -+ PINCTRL_PIN(54, "gpio54"), -+ PINCTRL_PIN(55, "gpio55"), -+}; -+ -+/* -+ * All single-pin functions can be mapped to any GPIO, however pinmux applies -+ * functions to pin groups and only those groups declared as supporting that -+ * function. To make this work we must put each pin in its own dummy group so -+ * that the functions can be described as applying to all pins. -+ * We use the same name as in the datasheet. -+ */ -+static const char * const mlxbf3_pinctrl_single_group_names[] = { -+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", -+ "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15", -+ "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23", -+ "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", -+ "gpio32", "gpio33", "gpio34", "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", -+ "gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", -+ "gpio48", "gpio49", "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", -+}; -+ -+static int mlxbf3_get_groups_count(struct pinctrl_dev *pctldev) -+{ -+ /* Number single-pin groups */ -+ return MLXBF3_MAX_GPIO_PINS; -+} -+ -+static const char *mlxbf3_get_group_name(struct pinctrl_dev *pctldev, -+ unsigned int selector) -+{ -+ return mlxbf3_pinctrl_single_group_names[selector]; -+} -+ -+static int mlxbf3_get_group_pins(struct pinctrl_dev *pctldev, -+ unsigned int selector, -+ const unsigned int **pins, -+ unsigned int *num_pins) -+{ -+ /* return the dummy group for a single pin */ -+ *pins = &selector; -+ *num_pins = 1; -+ -+ return 0; -+} -+ -+static const struct pinctrl_ops mlxbf3_pinctrl_group_ops = { -+ .get_groups_count = mlxbf3_get_groups_count, -+ .get_group_name = mlxbf3_get_group_name, -+ .get_group_pins = mlxbf3_get_group_pins, -+}; -+ -+/* -+ * Only 2 functions are supported and they apply to all pins: -+ * 1) Default hardware functionality -+ * 2) Software controlled GPIO -+ */ -+static const char * const mlxbf3_gpiofunc_group_names[] = { "swctrl" }; -+static const char * const mlxbf3_hwfunc_group_names[] = { "hwctrl" }; -+ -+struct pinfunction mlxbf3_pmx_funcs[] = { -+ PINCTRL_PINFUNCTION("hwfunc", mlxbf3_hwfunc_group_names, 1), -+ PINCTRL_PINFUNCTION("gpiofunc", mlxbf3_gpiofunc_group_names, 1), -+}; -+ -+static int mlxbf3_pmx_get_funcs_count(struct pinctrl_dev *pctldev) -+{ -+ return ARRAY_SIZE(mlxbf3_pmx_funcs); -+} -+ -+static const char *mlxbf3_pmx_get_func_name(struct pinctrl_dev *pctldev, -+ unsigned int selector) -+{ -+ return mlxbf3_pmx_funcs[selector].name; -+} -+ -+static int mlxbf3_pmx_get_groups(struct pinctrl_dev *pctldev, -+ unsigned int selector, -+ const char * const **groups, -+ unsigned int * const num_groups) -+{ -+ *groups = mlxbf3_pmx_funcs[selector].groups; -+ *num_groups = MLXBF3_MAX_GPIO_PINS; -+ -+ return 0; -+} -+ -+static int mlxbf3_pmx_set(struct pinctrl_dev *pctldev, -+ unsigned int selector, -+ unsigned int group) -+{ -+ struct mlxbf3_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev); -+ -+ if (selector == MLXBF3_GPIO_HW_MODE) { -+ if (group < MLXBF3_NGPIOS_GPIO0) -+ writel(BIT(group), priv->fw_ctrl_clr0); -+ else -+ writel(BIT(group % MLXBF3_NGPIOS_GPIO0), priv->fw_ctrl_clr1); -+ } -+ -+ if (selector == MLXBF3_GPIO_SW_MODE) { -+ if (group < MLXBF3_NGPIOS_GPIO0) -+ writel(BIT(group), priv->fw_ctrl_set0); -+ else -+ writel(BIT(group % MLXBF3_NGPIOS_GPIO0), priv->fw_ctrl_set1); -+ } -+ -+ return 0; -+} -+ -+static int mlxbf3_gpio_request_enable(struct pinctrl_dev *pctldev, -+ struct pinctrl_gpio_range *range, -+ unsigned int offset) -+{ -+ struct mlxbf3_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev); -+ -+ if (offset < MLXBF3_NGPIOS_GPIO0) -+ writel(BIT(offset), priv->fw_ctrl_set0); -+ else -+ writel(BIT(offset % MLXBF3_NGPIOS_GPIO0), priv->fw_ctrl_set1); -+ -+ return 0; -+} -+ -+static void mlxbf3_gpio_disable_free(struct pinctrl_dev *pctldev, -+ struct pinctrl_gpio_range *range, -+ unsigned int offset) -+{ -+ struct mlxbf3_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev); -+ -+ /* disable GPIO functionality by giving control back to hardware */ -+ if (offset < MLXBF3_NGPIOS_GPIO0) -+ writel(BIT(offset), priv->fw_ctrl_clr0); -+ else -+ writel(BIT(offset % MLXBF3_NGPIOS_GPIO0), priv->fw_ctrl_clr1); -+} -+ -+static const struct pinmux_ops mlxbf3_pmx_ops = { -+ .get_functions_count = mlxbf3_pmx_get_funcs_count, -+ .get_function_name = mlxbf3_pmx_get_func_name, -+ .get_function_groups = mlxbf3_pmx_get_groups, -+ .set_mux = mlxbf3_pmx_set, -+ .gpio_request_enable = mlxbf3_gpio_request_enable, -+ .gpio_disable_free = mlxbf3_gpio_disable_free, -+}; -+ -+static struct pinctrl_desc mlxbf3_pin_desc = { -+ .name = "pinctrl-mlxbf3", -+ .pins = mlxbf3_pins, -+ .npins = ARRAY_SIZE(mlxbf3_pins), -+ .pctlops = &mlxbf3_pinctrl_group_ops, -+ .pmxops = &mlxbf3_pmx_ops, -+ .owner = THIS_MODULE, -+}; -+ -+static_assert(ARRAY_SIZE(mlxbf3_pinctrl_single_group_names) == MLXBF3_MAX_GPIO_PINS); -+ -+static int mlxbf3_pinctrl_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct mlxbf3_pinctrl *priv; -+ int ret; -+ -+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); -+ if (!priv) -+ return -ENOMEM; -+ -+ priv->dev = &pdev->dev; -+ -+ priv->fw_ctrl_set0 = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(priv->fw_ctrl_set0)) -+ return PTR_ERR(priv->fw_ctrl_set0); -+ -+ priv->fw_ctrl_clr0 = devm_platform_ioremap_resource(pdev, 1); -+ if (IS_ERR(priv->fw_ctrl_set0)) -+ return PTR_ERR(priv->fw_ctrl_set0); -+ -+ priv->fw_ctrl_set1 = devm_platform_ioremap_resource(pdev, 2); -+ if (IS_ERR(priv->fw_ctrl_set0)) -+ return PTR_ERR(priv->fw_ctrl_set0); -+ -+ priv->fw_ctrl_clr1 = devm_platform_ioremap_resource(pdev, 3); -+ if (IS_ERR(priv->fw_ctrl_set0)) -+ return PTR_ERR(priv->fw_ctrl_set0); -+ -+ ret = devm_pinctrl_register_and_init(dev, -+ &mlxbf3_pin_desc, -+ priv, -+ &priv->pctl); -+ if (ret) -+ return dev_err_probe(dev, ret, "Failed to register pinctrl\n"); -+ -+ ret = pinctrl_enable(priv->pctl); -+ if (ret) -+ return dev_err_probe(dev, ret, "Failed to enable pinctrl\n"); -+ -+ pinctrl_add_gpio_ranges(priv->pctl, mlxbf3_pinctrl_gpio_ranges, 2); -+ -+ return 0; -+} -+ -+static const struct acpi_device_id mlxbf3_pinctrl_acpi_ids[] = { -+ { "MLNXBF34", 0 }, -+ {} -+}; -+MODULE_DEVICE_TABLE(acpi, mlxbf3_pinctrl_acpi_ids); -+ -+static struct platform_driver mlxbf3_pinctrl_driver = { -+ .driver = { -+ .name = "pinctrl-mlxbf3", -+ .acpi_match_table = mlxbf3_pinctrl_acpi_ids, -+ }, -+ .probe = mlxbf3_pinctrl_probe, -+}; -+module_platform_driver(mlxbf3_pinctrl_driver); -+ -+MODULE_DESCRIPTION("NVIDIA pinctrl driver"); -+MODULE_AUTHOR("Asmaa Mnebhi "); -+MODULE_LICENSE("Dual BSD/GPL"); --- -2.20.1 - diff --git a/patch/0063-gpio-mlxbf3-Add-gpio-driver-support.patch b/patch/0063-gpio-mlxbf3-Add-gpio-driver-support.patch deleted file mode 100644 index e9b14960a169..000000000000 --- a/patch/0063-gpio-mlxbf3-Add-gpio-driver-support.patch +++ /dev/null @@ -1,314 +0,0 @@ -From 8623b9727f7dc08fef553dbdc2be96641929b7cc Mon Sep 17 00:00:00 2001 -From: Asmaa Mnebhi -Date: Wed, 15 Mar 2023 17:50:26 -0400 -Subject: [PATCH backport 6.1.42 1/1] gpio: mlxbf3: Add gpio driver support - -Add support for the BlueField-3 SoC GPIO driver. -This driver configures and handles GPIO interrupts. It also enables a user -to manipulate certain GPIO pins via libgpiod tools or other kernel drivers. -The usables pins are defined via the "gpio-reserved-ranges" property. - -Signed-off-by: Asmaa Mnebhi -Reviewed-by: Andy Shevchenko -Reviewed-by: Linus Walleij -Signed-off-by: Bartosz Golaszewski ---- - drivers/gpio/Kconfig | 13 ++ - drivers/gpio/Makefile | 1 + - drivers/gpio/gpio-mlxbf3.c | 248 +++++++++++++++++++++++++++++++++++++ - 3 files changed, 262 insertions(+) - create mode 100644 drivers/gpio/gpio-mlxbf3.c - -diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig -index 3e8e5f4ffa59..aef128b3a1c2 100644 ---- a/drivers/gpio/Kconfig -+++ b/drivers/gpio/Kconfig -@@ -1532,6 +1532,19 @@ config GPIO_MLXBF2 - help - Say Y here if you want GPIO support on Mellanox BlueField 2 SoC. - -+config GPIO_MLXBF3 -+ tristate "Mellanox BlueField 3 SoC GPIO" -+ depends on (MELLANOX_PLATFORM && ARM64) || COMPILE_TEST -+ select GPIO_GENERIC -+ select GPIOLIB_IRQCHIP -+ help -+ Say Y if you want GPIO support on Mellanox BlueField 3 SoC. -+ This GPIO controller supports interrupt handling and enables the -+ manipulation of certain GPIO pins. -+ This controller should be used in parallel with pinctrl-mlxbf3 to -+ control the desired GPIOs. -+ This driver can also be built as a module called mlxbf3-gpio. -+ - config GPIO_ML_IOH - tristate "OKI SEMICONDUCTOR ML7213 IOH GPIO support" - depends on X86 || COMPILE_TEST -diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile -index 29e3beb6548c..c5e86fd24d2c 100644 ---- a/drivers/gpio/Makefile -+++ b/drivers/gpio/Makefile -@@ -98,6 +98,7 @@ obj-$(CONFIG_GPIO_MERRIFIELD) += gpio-merrifield.o - obj-$(CONFIG_GPIO_ML_IOH) += gpio-ml-ioh.o - obj-$(CONFIG_GPIO_MLXBF) += gpio-mlxbf.o - obj-$(CONFIG_GPIO_MLXBF2) += gpio-mlxbf2.o -+obj-$(CONFIG_GPIO_MLXBF3) += gpio-mlxbf3.o - obj-$(CONFIG_GPIO_MM_LANTIQ) += gpio-mm-lantiq.o - obj-$(CONFIG_GPIO_MOCKUP) += gpio-mockup.o - obj-$(CONFIG_GPIO_MOXTET) += gpio-moxtet.o -diff --git a/drivers/gpio/gpio-mlxbf3.c b/drivers/gpio/gpio-mlxbf3.c -new file mode 100644 -index 000000000000..e30cee108986 ---- /dev/null -+++ b/drivers/gpio/gpio-mlxbf3.c -@@ -0,0 +1,248 @@ -+// SPDX-License-Identifier: GPL-2.0-only or BSD-3-Clause -+/* Copyright (C) 2022 NVIDIA CORPORATION & AFFILIATES */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* -+ * There are 2 YU GPIO blocks: -+ * gpio[0]: HOST_GPIO0->HOST_GPIO31 -+ * gpio[1]: HOST_GPIO32->HOST_GPIO55 -+ */ -+#define MLXBF3_GPIO_MAX_PINS_PER_BLOCK 32 -+ -+/* -+ * fw_gpio[x] block registers and their offset -+ */ -+#define MLXBF_GPIO_FW_OUTPUT_ENABLE_SET 0x00 -+#define MLXBF_GPIO_FW_DATA_OUT_SET 0x04 -+ -+#define MLXBF_GPIO_FW_OUTPUT_ENABLE_CLEAR 0x00 -+#define MLXBF_GPIO_FW_DATA_OUT_CLEAR 0x04 -+ -+#define MLXBF_GPIO_CAUSE_RISE_EN 0x00 -+#define MLXBF_GPIO_CAUSE_FALL_EN 0x04 -+#define MLXBF_GPIO_READ_DATA_IN 0x08 -+ -+#define MLXBF_GPIO_CAUSE_OR_CAUSE_EVTEN0 0x00 -+#define MLXBF_GPIO_CAUSE_OR_EVTEN0 0x14 -+#define MLXBF_GPIO_CAUSE_OR_CLRCAUSE 0x18 -+ -+struct mlxbf3_gpio_context { -+ struct gpio_chip gc; -+ -+ /* YU GPIO block address */ -+ void __iomem *gpio_set_io; -+ void __iomem *gpio_clr_io; -+ void __iomem *gpio_io; -+ -+ /* YU GPIO cause block address */ -+ void __iomem *gpio_cause_io; -+}; -+ -+static void mlxbf3_gpio_irq_enable(struct irq_data *irqd) -+{ -+ struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); -+ struct mlxbf3_gpio_context *gs = gpiochip_get_data(gc); -+ irq_hw_number_t offset = irqd_to_hwirq(irqd); -+ unsigned long flags; -+ u32 val; -+ -+ gpiochip_enable_irq(gc, offset); -+ -+ raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags); -+ writel(BIT(offset), gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_CLRCAUSE); -+ -+ val = readl(gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0); -+ val |= BIT(offset); -+ writel(val, gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0); -+ raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags); -+} -+ -+static void mlxbf3_gpio_irq_disable(struct irq_data *irqd) -+{ -+ struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); -+ struct mlxbf3_gpio_context *gs = gpiochip_get_data(gc); -+ irq_hw_number_t offset = irqd_to_hwirq(irqd); -+ unsigned long flags; -+ u32 val; -+ -+ raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags); -+ val = readl(gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0); -+ val &= ~BIT(offset); -+ writel(val, gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0); -+ raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags); -+ -+ gpiochip_disable_irq(gc, offset); -+} -+ -+static irqreturn_t mlxbf3_gpio_irq_handler(int irq, void *ptr) -+{ -+ struct mlxbf3_gpio_context *gs = ptr; -+ struct gpio_chip *gc = &gs->gc; -+ unsigned long pending; -+ u32 level; -+ -+ pending = readl(gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_CAUSE_EVTEN0); -+ writel(pending, gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_CLRCAUSE); -+ -+ for_each_set_bit(level, &pending, gc->ngpio) -+ generic_handle_domain_irq(gc->irq.domain, level); -+ -+ return IRQ_RETVAL(pending); -+} -+ -+static int -+mlxbf3_gpio_irq_set_type(struct irq_data *irqd, unsigned int type) -+{ -+ struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); -+ struct mlxbf3_gpio_context *gs = gpiochip_get_data(gc); -+ irq_hw_number_t offset = irqd_to_hwirq(irqd); -+ unsigned long flags; -+ u32 val; -+ -+ raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags); -+ -+ switch (type & IRQ_TYPE_SENSE_MASK) { -+ case IRQ_TYPE_EDGE_BOTH: -+ val = readl(gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN); -+ val |= BIT(offset); -+ writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN); -+ val = readl(gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN); -+ val |= BIT(offset); -+ writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN); -+ break; -+ case IRQ_TYPE_EDGE_RISING: -+ val = readl(gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN); -+ val |= BIT(offset); -+ writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN); -+ break; -+ case IRQ_TYPE_EDGE_FALLING: -+ val = readl(gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN); -+ val |= BIT(offset); -+ writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN); -+ break; -+ default: -+ raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags); -+ return -EINVAL; -+ } -+ -+ raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags); -+ -+ irq_set_handler_locked(irqd, handle_edge_irq); -+ -+ return 0; -+} -+ -+/* This function needs to be defined for handle_edge_irq() */ -+static void mlxbf3_gpio_irq_ack(struct irq_data *data) -+{ -+} -+ -+static const struct irq_chip gpio_mlxbf3_irqchip = { -+ .name = "MLNXBF33", -+ .irq_ack = mlxbf3_gpio_irq_ack, -+ .irq_set_type = mlxbf3_gpio_irq_set_type, -+ .irq_enable = mlxbf3_gpio_irq_enable, -+ .irq_disable = mlxbf3_gpio_irq_disable, -+ .flags = IRQCHIP_IMMUTABLE, -+ GPIOCHIP_IRQ_RESOURCE_HELPERS, -+}; -+ -+static int mlxbf3_gpio_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct mlxbf3_gpio_context *gs; -+ struct gpio_irq_chip *girq; -+ struct gpio_chip *gc; -+ int ret, irq; -+ -+ gs = devm_kzalloc(dev, sizeof(*gs), GFP_KERNEL); -+ if (!gs) -+ return -ENOMEM; -+ -+ gs->gpio_io = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(gs->gpio_io)) -+ return PTR_ERR(gs->gpio_io); -+ -+ gs->gpio_cause_io = devm_platform_ioremap_resource(pdev, 1); -+ if (IS_ERR(gs->gpio_cause_io)) -+ return PTR_ERR(gs->gpio_cause_io); -+ -+ gs->gpio_set_io = devm_platform_ioremap_resource(pdev, 2); -+ if (IS_ERR(gs->gpio_set_io)) -+ return PTR_ERR(gs->gpio_set_io); -+ -+ gs->gpio_clr_io = devm_platform_ioremap_resource(pdev, 3); -+ if (IS_ERR(gs->gpio_clr_io)) -+ return PTR_ERR(gs->gpio_clr_io); -+ gc = &gs->gc; -+ -+ ret = bgpio_init(gc, dev, 4, -+ gs->gpio_io + MLXBF_GPIO_READ_DATA_IN, -+ gs->gpio_set_io + MLXBF_GPIO_FW_DATA_OUT_SET, -+ gs->gpio_clr_io + MLXBF_GPIO_FW_DATA_OUT_CLEAR, -+ gs->gpio_set_io + MLXBF_GPIO_FW_OUTPUT_ENABLE_SET, -+ gs->gpio_clr_io + MLXBF_GPIO_FW_OUTPUT_ENABLE_CLEAR, 0); -+ -+ gc->request = gpiochip_generic_request; -+ gc->free = gpiochip_generic_free; -+ gc->owner = THIS_MODULE; -+ -+ irq = platform_get_irq(pdev, 0); -+ if (irq >= 0) { -+ girq = &gs->gc.irq; -+ gpio_irq_chip_set_chip(girq, &gpio_mlxbf3_irqchip); -+ girq->default_type = IRQ_TYPE_NONE; -+ /* This will let us handle the parent IRQ in the driver */ -+ girq->num_parents = 0; -+ girq->parents = NULL; -+ girq->parent_handler = NULL; -+ girq->handler = handle_bad_irq; -+ -+ /* -+ * Directly request the irq here instead of passing -+ * a flow-handler because the irq is shared. -+ */ -+ ret = devm_request_irq(dev, irq, mlxbf3_gpio_irq_handler, -+ IRQF_SHARED, dev_name(dev), gs); -+ if (ret) -+ return dev_err_probe(dev, ret, "failed to request IRQ"); -+ } -+ -+ platform_set_drvdata(pdev, gs); -+ -+ ret = devm_gpiochip_add_data(dev, &gs->gc, gs); -+ if (ret) -+ dev_err_probe(dev, ret, "Failed adding memory mapped gpiochip\n"); -+ -+ return 0; -+} -+ -+static const struct acpi_device_id mlxbf3_gpio_acpi_match[] = { -+ { "MLNXBF33", 0 }, -+ {} -+}; -+MODULE_DEVICE_TABLE(acpi, mlxbf3_gpio_acpi_match); -+ -+static struct platform_driver mlxbf3_gpio_driver = { -+ .driver = { -+ .name = "mlxbf3_gpio", -+ .acpi_match_table = mlxbf3_gpio_acpi_match, -+ }, -+ .probe = mlxbf3_gpio_probe, -+}; -+module_platform_driver(mlxbf3_gpio_driver); -+ -+MODULE_DESCRIPTION("NVIDIA BlueField-3 GPIO Driver"); -+MODULE_AUTHOR("Asmaa Mnebhi "); -+MODULE_LICENSE("Dual BSD/GPL"); --- -2.25.1 - diff --git a/patch/0064-pinctrl-mlxbf3-set-varaiable-mlxbf3_pmx_funcs-storag.patch b/patch/0064-pinctrl-mlxbf3-set-varaiable-mlxbf3_pmx_funcs-storag.patch deleted file mode 100644 index 388279b96a18..000000000000 --- a/patch/0064-pinctrl-mlxbf3-set-varaiable-mlxbf3_pmx_funcs-storag.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 00cba650c86f494b4a5905d89d304fef2380b0b7 Mon Sep 17 00:00:00 2001 -From: Tom Rix -Date: Mon, 3 Apr 2023 20:45:01 -0400 -Subject: [PATCH backport 6.1.42 2/2] pinctrl: mlxbf3: set varaiable - mlxbf3_pmx_funcs storage-class-specifier to static - -smatch reports -drivers/pinctrl/pinctrl-mlxbf3.c:162:20: warning: symbol - 'mlxbf3_pmx_funcs' was not declared. Should it be static? - -This variable is only used in one file so it should be static. - -Signed-off-by: Tom Rix -Link: https://lore.kernel.org/r/20230404004501.1913144-1-trix@redhat.com -Signed-off-by: Linus Walleij ---- - drivers/pinctrl/pinctrl-mlxbf3.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/pinctrl/pinctrl-mlxbf3.c b/drivers/pinctrl/pinctrl-mlxbf3.c -index 3698f7bbd88d..d9944e6a0af9 100644 ---- a/drivers/pinctrl/pinctrl-mlxbf3.c -+++ b/drivers/pinctrl/pinctrl-mlxbf3.c -@@ -159,7 +159,7 @@ static const struct pinctrl_ops mlxbf3_pinctrl_group_ops = { - static const char * const mlxbf3_gpiofunc_group_names[] = { "swctrl" }; - static const char * const mlxbf3_hwfunc_group_names[] = { "hwctrl" }; - --struct pinfunction mlxbf3_pmx_funcs[] = { -+static struct pinfunction mlxbf3_pmx_funcs[] = { - PINCTRL_PINFUNCTION("hwfunc", mlxbf3_hwfunc_group_names, 1), - PINCTRL_PINFUNCTION("gpiofunc", mlxbf3_gpiofunc_group_names, 1), - }; --- -2.25.1 - diff --git a/patch/0087-platform-mellanox-indicate-deferred-I2C-bus-creation.patch b/patch/0087-platform-mellanox-indicate-deferred-I2C-bus-creation.patch new file mode 100644 index 000000000000..0f602a94048a --- /dev/null +++ b/patch/0087-platform-mellanox-indicate-deferred-I2C-bus-creation.patch @@ -0,0 +1,31 @@ +From ab5040e2b99cc3eb57eaa266b90877bcc38c28ed Mon Sep 17 00:00:00 2001 +From: Michael Shych +Date: Wed, 29 Nov 2023 13:12:38 +0000 +Subject: [PATCH v1 1/1] platform: mellanox: indicate deferred I2C bus creation + for a hot-plug driver + +It fixes timing issue when during initialization hot-plug driver +attempts to attach a component to I2C bus, which is still not created. +Setting deferred bus parameter will force hot-plug driver to wait +until the bus is available. + +Signed-off-by: Michael Shych +--- + drivers/platform/mellanox/nvsw-sn2201.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/platform/mellanox/nvsw-sn2201.c b/drivers/platform/mellanox/nvsw-sn2201.c +index 65b677690..79e4d0619 100644 +--- a/drivers/platform/mellanox/nvsw-sn2201.c ++++ b/drivers/platform/mellanox/nvsw-sn2201.c +@@ -520,6 +520,7 @@ struct mlxreg_core_hotplug_platform_data nvsw_sn2201_hotplug = { + .counter = ARRAY_SIZE(nvsw_sn2201_items), + .cell = NVSW_SN2201_SYS_INT_STATUS_OFFSET, + .mask = NVSW_SN2201_CPLD_AGGR_MASK_DEF, ++ .deferred_nr = NVSW_SN2201_2ND_MUX_CH3_NR, + }; + + /* SN2201 static devices. */ +-- +2.14.1 + diff --git a/patch/8000-mlxsw-Use-weak-reverse-dependencies-for-firmware-fla.patch b/patch/8000-mlxsw-Use-weak-reverse-dependencies-for-firmware-fla.patch new file mode 100644 index 000000000000..ba8f2fd77720 --- /dev/null +++ b/patch/8000-mlxsw-Use-weak-reverse-dependencies-for-firmware-fla.patch @@ -0,0 +1,34 @@ +From 646a7ca330eddb18e915380c9e8296a8cbce3c81 Mon Sep 17 00:00:00 2001 +From: Vadim Pasternak +Date: Wed, 20 Oct 2021 09:49:28 +0000 +Subject: [PATCH backport 6.1.42 40/85] mlxsw: Use weak reverse dependencies + for firmware flashing selection + +Replace configuration options "select" by "imply". It allows to set +'MLXFW' symbol to 'n' from a direct dependency or with a visible +prompt. + +User might wish to disable this option in case only 'mlxsw_minimal' is +configured, since it does not support firmware flashing. + +Signed-off-by: Vadim Pasternak +--- + drivers/net/ethernet/mellanox/mlxsw/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/net/ethernet/mellanox/mlxsw/Kconfig b/drivers/net/ethernet/mellanox/mlxsw/Kconfig +index a510bf2cff2f..efc7ec8fa33c 100644 +--- a/drivers/net/ethernet/mellanox/mlxsw/Kconfig ++++ b/drivers/net/ethernet/mellanox/mlxsw/Kconfig +@@ -6,7 +6,7 @@ + config MLXSW_CORE + tristate "Mellanox Technologies Switch ASICs support" + select NET_DEVLINK +- select MLXFW ++ imply MLXFW + select AUXILIARY_BUS + help + This driver supports Mellanox Technologies Switch ASICs family. +-- +2.20.1 + diff --git a/patch/8004-mlxsw-minimal-Downstream-Ignore-error-reading-SPAD-r.patch b/patch/8004-mlxsw-minimal-Downstream-Ignore-error-reading-SPAD-r.patch new file mode 100644 index 000000000000..3a220713e0ff --- /dev/null +++ b/patch/8004-mlxsw-minimal-Downstream-Ignore-error-reading-SPAD-r.patch @@ -0,0 +1,36 @@ +From a742d55ed36a0bd3b6346563665b951dad9ad469 Mon Sep 17 00:00:00 2001 +From: root +Date: Tue, 5 Apr 2022 21:35:55 +0300 +Subject: [PATH backport v6.1 2/3] mlxsw: minimal: Downstream: Ignore error + reading SPAD register + +SPAD register is not supported for IB systems. + +Signed-off-by: Vadim Pasternak +--- + drivers/net/ethernet/mellanox/mlxsw/minimal.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/net/ethernet/mellanox/mlxsw/minimal.c b/drivers/net/ethernet/mellanox/mlxsw/minimal.c +index 15116d9305f8..7396b37bc880 100644 +--- a/drivers/net/ethernet/mellanox/mlxsw/minimal.c ++++ b/drivers/net/ethernet/mellanox/mlxsw/minimal.c +@@ -53,6 +53,7 @@ struct mlxsw_m_port { + + static int mlxsw_m_base_mac_get(struct mlxsw_m *mlxsw_m) + { ++#if 0 + char spad_pl[MLXSW_REG_SPAD_LEN] = {0}; + int err; + +@@ -60,6 +61,7 @@ static int mlxsw_m_base_mac_get(struct mlxsw_m *mlxsw_m) + if (err) + return err; + mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_m->base_mac); ++#endif + return 0; + } + +-- +2.20.1 + diff --git a/patch/8010-mlxsw-i2c-Downstream-Add-retry-mechanism-for-failed-.patch b/patch/8010-mlxsw-i2c-Downstream-Add-retry-mechanism-for-failed-.patch new file mode 100644 index 000000000000..3351c1996035 --- /dev/null +++ b/patch/8010-mlxsw-i2c-Downstream-Add-retry-mechanism-for-failed-.patch @@ -0,0 +1,128 @@ +From 690d6ada04f5bd9a9a57edc7b67e311961fe134c Mon Sep 17 00:00:00 2001 +From: Vadim Pasternak +Date: Sun, 19 Nov 2023 13:22:27 +0000 +Subject: [PATCH v6.1 1/1] mlxsw: i2c: Downstream: Add retry mechanism for + failed transactions + +Sometimes I2C transactions could broken or non-completed because of +some noise on I2C line or because ASIC resources is busy handling +big amount of PCIe tarnsactions. + +Add re-try mechanism for re-sending transaction which was not properly +completed. +Retry up to three times and produce error log only in case the last try +is not successful. + +Signed-off-by: Vadim Pasternak +--- + drivers/net/ethernet/mellanox/mlxsw/i2c.c | 33 ++++++++++++++++------- + 1 file changed, 24 insertions(+), 9 deletions(-) + +diff --git a/drivers/net/ethernet/mellanox/mlxsw/i2c.c b/drivers/net/ethernet/mellanox/mlxsw/i2c.c +index 43140eccc8bb..90d7bfe2865c 100644 +--- a/drivers/net/ethernet/mellanox/mlxsw/i2c.c ++++ b/drivers/net/ethernet/mellanox/mlxsw/i2c.c +@@ -51,6 +51,7 @@ + #define MLXSW_I2C_BLK_MAX 100 + #define MLXSW_I2C_RETRY 5 + #define MLXSW_I2C_TIMEOUT_MSECS 5000 ++#define MLXSW_I2C_CMD_RETRY_FW_ERR 3 + #define MLXSW_I2C_MAX_DATA_SIZE 256 + + /* Driver can be initialized by kernel platform driver or from the user +@@ -78,6 +79,7 @@ + * @irq_work: interrupts work item; + * @irq: IRQ line number; + * @status: status to indicate chip reset or in-service update; ++ * @retry_cntr: retry counter for failed transaction; + */ + struct mlxsw_i2c { + struct { +@@ -95,6 +97,7 @@ struct mlxsw_i2c { + struct work_struct irq_work; + int irq; + u8 status; ++ int retry_cntr; + }; + + #define MLXSW_I2C_READ_MSG(_client, _addr_buf, _buf, _len) { \ +@@ -395,7 +398,8 @@ mlxsw_i2c_write(struct device *dev, size_t in_mbox_size, u8 *in_mbox, int num, + /* Prepare and write out Command Interface Register for transaction. */ + err = mlxsw_i2c_write_cmd(client, mlxsw_i2c, 0); + if (err) { +- dev_err(&client->dev, "Could not start transaction"); ++ if (mlxsw_i2c->retry_cntr == MLXSW_I2C_CMD_RETRY_FW_ERR) ++ dev_err(&client->dev, "Could not start transaction"); + err = -EIO; + goto mlxsw_i2c_write_exit; + } +@@ -403,14 +407,16 @@ mlxsw_i2c_write(struct device *dev, size_t in_mbox_size, u8 *in_mbox, int num, + /* Wait until go bit is cleared. */ + err = mlxsw_i2c_wait_go_bit(client, mlxsw_i2c, p_status); + if (err) { +- dev_err(&client->dev, "HW semaphore is not released"); ++ if (mlxsw_i2c->retry_cntr == MLXSW_I2C_CMD_RETRY_FW_ERR) ++ dev_err(&client->dev, "HW semaphore is not released"); + goto mlxsw_i2c_write_exit; + } + + /* Validate transaction completion status. */ + if (*p_status) { +- dev_err(&client->dev, "Bad transaction completion status %x\n", +- *p_status); ++ if (mlxsw_i2c->retry_cntr == MLXSW_I2C_CMD_RETRY_FW_ERR) ++ dev_err(&client->dev, "Bad transaction completion status %x\n", ++ *p_status); + err = -EIO; + } + +@@ -440,14 +446,16 @@ mlxsw_i2c_cmd(struct device *dev, u16 opcode, u32 in_mod, size_t in_mbox_size, + /* Do not run transaction if chip is in reset or in-service update state. */ + if (mlxsw_i2c->status) + return 0; +- ++retry: + if (in_mbox) { + reg_size = mlxsw_i2c_get_reg_size(in_mbox); + num = DIV_ROUND_UP(reg_size, mlxsw_i2c->block_size); + + if (mutex_lock_interruptible(&mlxsw_i2c->cmd.lock) < 0) { +- dev_err(&client->dev, "Could not acquire lock"); +- return -EINVAL; ++ if (mlxsw_i2c->retry_cntr == MLXSW_I2C_CMD_RETRY_FW_ERR) ++ dev_err(&client->dev, "Could not acquire lock"); ++ err = -EINVAL; ++ goto cmd_retry; + } + + err = mlxsw_i2c_write(dev, reg_size, in_mbox, num, status); +@@ -465,8 +473,10 @@ mlxsw_i2c_cmd(struct device *dev, u16 opcode, u32 in_mod, size_t in_mbox_size, + num = DIV_ROUND_UP(reg_size, mlxsw_i2c->block_size); + + if (mutex_lock_interruptible(&mlxsw_i2c->cmd.lock) < 0) { +- dev_err(&client->dev, "Could not acquire lock"); +- return -EINVAL; ++ if (mlxsw_i2c->retry_cntr == MLXSW_I2C_CMD_RETRY_FW_ERR) ++ dev_err(&client->dev, "Could not acquire lock"); ++ err = -EINVAL; ++ goto cmd_retry; + } + + err = mlxsw_i2c_write_init_cmd(client, mlxsw_i2c, opcode, +@@ -513,8 +523,13 @@ mlxsw_i2c_cmd(struct device *dev, u16 opcode, u32 in_mod, size_t in_mbox_size, + + cmd_fail: + mutex_unlock(&mlxsw_i2c->cmd.lock); ++cmd_retry: + if (mlxsw_i2c_cmd_status_verify(&client->dev, mlxsw_i2c, *status)) + err = 0; ++ else if (mlxsw_i2c->retry_cntr++ < MLXSW_I2C_CMD_RETRY_FW_ERR) ++ goto retry; ++ mlxsw_i2c->retry_cntr = 0; ++ + return err; + } + +-- +2.20.1 + diff --git a/patch/8011-mlxsw-minimal-Downstream-Disable-ethtool-interface.patch b/patch/8011-mlxsw-minimal-Downstream-Disable-ethtool-interface.patch new file mode 100644 index 000000000000..16967d44a5d4 --- /dev/null +++ b/patch/8011-mlxsw-minimal-Downstream-Disable-ethtool-interface.patch @@ -0,0 +1,51 @@ +From c10df5bb36bfe0b73a4b3195e27f7c71b4e4caf1 Mon Sep 17 00:00:00 2001 +From: Vadim Pasternak +Date: Sun, 14 Jan 2024 16:46:03 +0000 +Subject: [PATCH v6.1 1/1] mlxsw: minimal: Downstream: Disable ethtool + interface + +Disable 'ethtool' interface, since it is un-used and just created +un-necessary 'netdevice' interfaces. + +Signed-off-by: Vadim Pasternak +--- + drivers/net/ethernet/mellanox/mlxsw/core_env.c | 1 + + drivers/net/ethernet/mellanox/mlxsw/minimal.c | 3 +++ + 2 files changed, 4 insertions(+) + +diff --git a/drivers/net/ethernet/mellanox/mlxsw/core_env.c b/drivers/net/ethernet/mellanox/mlxsw/core_env.c +index 550475a108ef..c42eed1209a1 100644 +--- a/drivers/net/ethernet/mellanox/mlxsw/core_env.c ++++ b/drivers/net/ethernet/mellanox/mlxsw/core_env.c +@@ -1403,6 +1403,7 @@ int mlxsw_env_init(struct mlxsw_core *mlxsw_core, + if (err) + goto err_linecards_event_ops_register; + ++ return 0; + err = mlxsw_env_temp_warn_event_register(mlxsw_core); + if (err) + goto err_temp_warn_event_register; +diff --git a/drivers/net/ethernet/mellanox/mlxsw/minimal.c b/drivers/net/ethernet/mellanox/mlxsw/minimal.c +index 7396b37bc880..5365e6984236 100644 +--- a/drivers/net/ethernet/mellanox/mlxsw/minimal.c ++++ b/drivers/net/ethernet/mellanox/mlxsw/minimal.c +@@ -532,6 +532,8 @@ static int mlxsw_m_ports_create(struct mlxsw_m *mlxsw_m) + { + int err; + ++ return 0; ++ + /* Fill out module to local port mapping array */ + err = mlxsw_m_ports_module_map(mlxsw_m); + if (err) +@@ -553,6 +555,7 @@ static int mlxsw_m_ports_create(struct mlxsw_m *mlxsw_m) + + static void mlxsw_m_ports_remove(struct mlxsw_m *mlxsw_m) + { ++ return; + mlxsw_m_linecard_ports_remove(mlxsw_m, 0); + } + +-- +2.20.1 + diff --git a/patch/kconfig-inclusions b/patch/kconfig-inclusions index 5bb2aea0bc18..93bc9c811fcd 100644 --- a/patch/kconfig-inclusions +++ b/patch/kconfig-inclusions @@ -5,7 +5,6 @@ CONFIG_LOG_BUF_SHIFT=20 [amd64] CONFIG_SATA_MOBILE_LPM_POLICY=1 - # For Arista CONFIG_I2C_MUX_PCA9541=m CONFIG_SENSORS_MAX6697=m @@ -71,7 +70,6 @@ CONFIG_MLX_PLATFORM=m CONFIG_NET_DEVLINK=y CONFIG_I2C_MUX_REG=m CONFIG_I2C_MUX_MLXCPLD=m -CONFIG_REGMAP_I2C=m CONFIG_IIO_SYSFS_TRIGGER=m CONFIG_NVME_HWMON=y CONFIG_MLXSW_CORE_HWMON=y @@ -89,6 +87,7 @@ CONFIG_SENSORS_TPS53679=m CONFIG_SENSORS_XDPE122=m CONFIG_SENSORS_MP2975=m CONFIG_SENSORS_MP2888=m +CONFIG_SENSORS_MP2891=m CONFIG_CPU_THERMAL=y CONFIG_IGB_HWMON=y CONFIG_MFD_CORE=y @@ -123,7 +122,6 @@ CONFIG_SENSORS_LTC2945=m CONFIG_SENSORS_TPS40422=m CONFIG_SPI_INTEL_PLATFORM=m CONFIG_SPI_INTEL=m - # For pensando CONFIG_IONIC=m @@ -207,3 +205,4 @@ CONFIG_MMC_DW_BLUEFIELD=y CONFIG_EFIVAR_FS=y [mellanox-arm64] + diff --git a/patch/series b/patch/series index 5c6a6e9f7a57..a0686a5c38e2 100755 --- a/patch/series +++ b/patch/series @@ -114,22 +114,33 @@ Support-for-fullcone-nat.patch 0039-mlxsw-reg-Limit-MTBR-register-payload-to-a-single-da.patch 0040-mlxsw-core-Extend-allowed-list-of-external-cooling-d.patch 0041-mlxsw-i2c-Utilize-standard-macros-for-dividing-buffe.patch +0042-hwmon-mlxreg-fan-Add-support-for-new-flavour-of-capa.patch 0043-hwmon-mlxreg-fan-Extend-number-of-supporetd-fans.patch +0044-leds-mlxreg-Add-support-for-new-flavour-of-capabilit.patch +0045-leds-mlxreg-Remove-code-for-amber-LED-colour.patch +0046-Extend-driver-to-support-Infineon-Digital-Multi-phas.patch +0047-dt-bindings-trivial-devices-Add-infineon-xdpe1a2g7.patch +0048-hwmon-pmbus-Add-support-for-MPS-Multi-phase-mp2891-c.patch +0049-dt-bindings-trivial-devices-Add-mps-mp2891.patch +0050-leds-mlxreg-Skip-setting-LED-color-during-initializa.patch 0051-platform-mellanox-mlxreg-hotplug-Allow-more-flexible.patch 0052-i2c-mux-Add-register-map-based-mux-driver.patch +0053-platform-mellanox-Add-support-for-dynamic-I2C-channe.patch +0054-platform-mellanox-Introduce-support-for-switches-equ.patch +0055-mellanox-Relocate-mlx-platform-driver.patch 0056-Documentation-ABI-Add-new-attribute-for-mlxreg-io-sy.patch -0057-Documentation-ABI-Add-new-attribute-for-mlxreg-io-sy.patch -0061-pinctrl-Introduce-struct-pinfunction-and-PINCTRL_PIN.patch -0062-pinctrl-mlxbf3-Add-pinctrl-driver-support.patch -0063-gpio-mlxbf3-Add-gpio-driver-support.patch -0064-pinctrl-mlxbf3-set-varaiable-mlxbf3_pmx_funcs-storag.patch 0085-hwmon-mlxreg-fan-Separate-methods-of-fan-setting-com.patch +0087-platform-mellanox-indicate-deferred-I2C-bus-creation.patch +8000-mlxsw-Use-weak-reverse-dependencies-for-firmware-fla.patch 8003-mlxsw-i2c-SONIC-ISSU-Prevent-transaction-execution-f.patch +8004-mlxsw-minimal-Downstream-Ignore-error-reading-SPAD-r.patch 8005-leds-leds-mlxreg-Downstream-Send-udev-event-from-led.patch 8006-i2c-mlxcpld-Downstream-WA-to-avoid-error-for-SMBUS-r.patch 8007-hwmon-mlxreg-fan-Downstream-Allow-fan-speed-setting-.patch 8008-hwmon-emc2305-Downstream-Allow-fan-speed-setting-gra.patch 8009-hwmon-mlxsw-Downstream-Allow-fan-speed-setting-granu.patch +8010-mlxsw-i2c-Downstream-Add-retry-mechanism-for-failed-.patch +8011-mlxsw-minimal-Downstream-Disable-ethtool-interface.patch ###-> mellanox_hw_mgmt-end # Cisco patches for 5.10 kernel