From 797dab4121bb38fd770e4d2a61f2201993ada031 Mon Sep 17 00:00:00 2001 From: Devesh Pathak <54966909+devpatha@users.noreply.github.com> Date: Thu, 18 Nov 2021 18:17:22 -0800 Subject: [PATCH] [muxorch] Bind all ports to drop ACL table (#2027) *BInd all physical ports to drop ACL table --- orchagent/muxorch.cpp | 20 +++++++++++++++++++- orchagent/muxorch.h | 1 + 2 files changed, 20 insertions(+), 1 deletion(-) diff --git a/orchagent/muxorch.cpp b/orchagent/muxorch.cpp index 6c0f67ff83be..f7af9f1f5c2f 100644 --- a/orchagent/muxorch.cpp +++ b/orchagent/muxorch.cpp @@ -793,9 +793,9 @@ void MuxAclHandler::createMuxAclTable(sai_object_id_t port, string strTable) acl_table.type = ACL_TABLE_DROP; acl_table.id = strTable; - acl_table.link(port); acl_table.stage = ACL_STAGE_INGRESS; gAclOrch->addAclTable(acl_table); + bindAllPorts(acl_table); } void MuxAclHandler::createMuxAclRule(shared_ptr rule, string strTable) @@ -820,6 +820,24 @@ void MuxAclHandler::createMuxAclRule(shared_ptr rule, string strTabl gAclOrch->addAclRule(rule, strTable); } +void MuxAclHandler::bindAllPorts(AclTable &acl_table) +{ + SWSS_LOG_ENTER(); + + auto allPorts = gPortsOrch->getAllPorts(); + for (auto &it: allPorts) + { + Port port = it.second; + if (port.m_type == Port::PHY) + { + SWSS_LOG_INFO("Binding port %" PRIx64 " to ACL table %s", port.m_port_id, acl_table.id.c_str()); + + acl_table.link(port.m_port_id); + acl_table.bind(port.m_port_id); + } + } +} + sai_object_id_t MuxOrch::createNextHopTunnel(std::string tunnelKey, swss::IpAddress& ipAddr) { auto it = mux_tunnel_nh_.find(ipAddr); diff --git a/orchagent/muxorch.h b/orchagent/muxorch.h index ed1f5bd4b1a7..fa8b0588301f 100644 --- a/orchagent/muxorch.h +++ b/orchagent/muxorch.h @@ -44,6 +44,7 @@ class MuxAclHandler private: void createMuxAclTable(sai_object_id_t port, string strTable); void createMuxAclRule(shared_ptr rule, string strTable); + void bindAllPorts(AclTable &acl_table); // class shared dict: ACL table name -> ACL table static std::map acl_table_;