Skip to content

Commit 266afd6

Browse files
ruck314ruck314
authored
Merge pull request #1196 from slaclab/pre-release
Release Candidate v2.51.0
2 parents 01fd4d7 + 5238204 commit 266afd6

25 files changed

+1073
-155
lines changed

‎axi/axi-stream/rtl/AxiStreamDeMux.vhd

+9-8
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,7 @@ use surf.AxiStreamPkg.all;
2626
entity AxiStreamDeMux is
2727
generic (
2828
TPD_G : time := 1 ns;
29+
RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset
2930
RST_ASYNC_G : boolean := false;
3031
NUM_MASTERS_G : integer range 1 to 256 := 12;
3132
MODE_G : string := "INDEXED"; -- Or "ROUTED" Or "DYNAMIC"
@@ -39,7 +40,7 @@ entity AxiStreamDeMux is
3940
axisRst : in sl;
4041
-- Dynamic Route Table (only used when MODE_G = "DYNAMIC")
4142
dynamicRouteMasks : in slv8Array(NUM_MASTERS_G-1 downto 0) := (others => "00000000");
42-
dynamicRouteDests : in slv8Array(NUM_MASTERS_G-1 downto 0) := (others => "00000000");
43+
dynamicRouteDests : in slv8Array(NUM_MASTERS_G-1 downto 0) := (others => "00000000");
4344
-- Slave
4445
sAxisMaster : in AxiStreamMasterType;
4546
sAxisSlave : out AxiStreamSlaveType;
@@ -139,7 +140,7 @@ begin
139140
sAxisSlave <= v.slave;
140141

141142
-- Reset
142-
if (RST_ASYNC_G = false and axisRst = '1') then
143+
if (RST_ASYNC_G = false and axisRst = RST_POLARITY_G) then
143144
v := REG_INIT_C;
144145
end if;
145146

@@ -151,14 +152,14 @@ begin
151152

152153
end process comb;
153154

154-
GEN_VEC :
155-
for i in (NUM_MASTERS_G-1) downto 0 generate
155+
GEN_VEC : for i in (NUM_MASTERS_G-1) downto 0 generate
156156

157157
U_Pipeline : entity surf.AxiStreamPipeline
158158
generic map (
159-
TPD_G => TPD_G,
160-
RST_ASYNC_G => RST_ASYNC_G,
161-
PIPE_STAGES_G => PIPE_STAGES_G)
159+
TPD_G => TPD_G,
160+
RST_POLARITY_G => RST_POLARITY_G,
161+
RST_ASYNC_G => RST_ASYNC_G,
162+
PIPE_STAGES_G => PIPE_STAGES_G)
162163
port map (
163164
axisClk => axisClk,
164165
axisRst => axisRst,
@@ -171,7 +172,7 @@ begin
171172

172173
seq : process (axisClk, axisRst) is
173174
begin
174-
if (RST_ASYNC_G and axisRst = '1') then
175+
if (RST_ASYNC_G and axisRst = RST_POLARITY_G) then
175176
r <= REG_INIT_C after TPD_G;
176177
elsif rising_edge(axisClk) then
177178
r <= rin after TPD_G;

‎axi/axi-stream/rtl/AxiStreamMux.vhd

+7-5
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,7 @@ use surf.AxiStreamPkg.all;
2727
entity AxiStreamMux is
2828
generic (
2929
TPD_G : time := 1 ns;
30+
RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset
3031
RST_ASYNC_G : boolean := false;
3132
PIPE_STAGES_G : integer range 0 to 16 := 0;
3233
NUM_SLAVES_G : integer range 1 to 256 := 4;
@@ -308,7 +309,7 @@ begin
308309
sAxisSlaves <= v.slaves;
309310

310311
-- Reset
311-
if (RST_ASYNC_G = false and axisRst = '1') then
312+
if (RST_ASYNC_G = false and axisRst = RST_POLARITY_G) then
312313
v := REG_INIT_C;
313314
end if;
314315

@@ -322,7 +323,7 @@ begin
322323

323324
seq : process (axisClk, axisRst) is
324325
begin
325-
if (RST_ASYNC_G) and (axisRst = '1') then
326+
if (RST_ASYNC_G) and (axisRst = RST_POLARITY_G) then
326327
r <= REG_INIT_C after TPD_G;
327328
elsif rising_edge(axisClk) then
328329
r <= rin after TPD_G;
@@ -332,9 +333,10 @@ begin
332333
-- Optional output pipeline registers to ease timing
333334
AxiStreamPipeline_1 : entity surf.AxiStreamPipeline
334335
generic map (
335-
TPD_G => TPD_G,
336-
RST_ASYNC_G => RST_ASYNC_G,
337-
PIPE_STAGES_G => PIPE_STAGES_G)
336+
TPD_G => TPD_G,
337+
RST_POLARITY_G => RST_POLARITY_G,
338+
RST_ASYNC_G => RST_ASYNC_G,
339+
PIPE_STAGES_G => PIPE_STAGES_G)
338340
port map (
339341
axisClk => axisClk,
340342
axisRst => axisRst,

‎axi/axi-stream/rtl/AxiStreamPipeline.vhd

+3-2
Original file line numberDiff line numberDiff line change
@@ -23,6 +23,7 @@ use surf.AxiStreamPkg.all;
2323
entity AxiStreamPipeline is
2424
generic (
2525
TPD_G : time := 1 ns;
26+
RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset
2627
RST_ASYNC_G : boolean := false;
2728
SIDE_BAND_WIDTH_G : positive := 1; -- General purpose sideband
2829
PIPE_STAGES_G : natural := 0);
@@ -148,7 +149,7 @@ begin
148149
mSideBand <= r.mSideBand(PIPE_STAGES_C);
149150

150151
-- Synchronous Reset
151-
if (RST_ASYNC_G = false and axisRst = '1') then
152+
if (RST_ASYNC_G = false and axisRst = RST_POLARITY_G) then
152153
v := REG_INIT_C;
153154
end if;
154155

@@ -159,7 +160,7 @@ begin
159160

160161
seq : process (axisClk, axisRst) is
161162
begin
162-
if (RST_ASYNC_G and axisRst = '1') then
163+
if (RST_ASYNC_G and axisRst = RST_POLARITY_G) then
163164
r <= REG_INIT_C after TPD_G;
164165
elsif rising_edge(axisClk) then
165166
r <= rin after TPD_G;

‎base/crc/rtl/Crc32.vhd

+7-6
Original file line numberDiff line numberDiff line change
@@ -34,15 +34,16 @@ use surf.CrcPkg.all;
3434
entity Crc32 is
3535
generic (
3636
TPD_G : time := 1 ns;
37+
RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset
3738
RST_ASYNC_G : boolean := false;
3839
BYTE_WIDTH_G : positive := 4;
3940
INPUT_REGISTER_G : boolean := true;
4041
CRC_INIT_G : slv(31 downto 0) := x"FFFFFFFF";
4142
CRC_POLY_G : slv(31 downto 0) := x"04C11DB7");
4243
port (
43-
crcPwrOnRst : in sl := '0';
44-
crcOut : out slv(31 downto 0); -- CRC output
45-
crcRem : out slv(31 downto 0); -- CRC interim remainder
44+
crcPwrOnRst : in sl := not RST_POLARITY_G;
45+
crcOut : out slv(31 downto 0); -- CRC output
46+
crcRem : out slv(31 downto 0); -- CRC interim remainder
4647
crcClk : in sl; -- system clock
4748
crcDataValid : in sl; -- indicate that new data arrived and CRC can be computed
4849
crcDataWidth : in slv(2 downto 0); -- indicate width in bytes minus 1, 0 - 1 byte, 1 - 2 bytes ... , 7 - 8 bytes
@@ -146,10 +147,10 @@ begin
146147

147148
seq : process (crcClk, crcPwrOnRst) is
148149
begin
149-
if (RST_ASYNC_G and crcPwrOnRst = '1') then
150+
if (RST_ASYNC_G and crcPwrOnRst = RST_POLARITY_G) then
150151
r <= REG_INIT_C after TPD_G;
151-
elsif (rising_edge(crcClk)) then
152-
if (RST_ASYNC_G = false and crcPwrOnRst = '1') then
152+
elsif (rising_edge(crcClk)) then
153+
if (RST_ASYNC_G = false and crcPwrOnRst = RST_POLARITY_G) then
153154
r <= REG_INIT_C after TPD_G;
154155
else
155156
r <= rin after TPD_G;

‎base/crc/rtl/Crc32Parallel.vhd

100755100644
+8-7
Original file line numberDiff line numberDiff line change
@@ -40,20 +40,21 @@ use surf.CrcPkg.all;
4040
entity Crc32Parallel is
4141
generic (
4242
TPD_G : time := 1 ns;
43+
RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset
4344
RST_ASYNC_G : boolean := false;
4445
BYTE_WIDTH_G : positive := 4;
4546
INPUT_REGISTER_G : boolean := true;
4647
CRC_INIT_G : slv(31 downto 0) := x"FFFFFFFF");
4748
port (
48-
crcPwrOnRst : in sl := '0';
49-
crcOut : out slv(31 downto 0); -- CRC output
50-
crcRem : out slv(31 downto 0); -- CRC interim remainder
49+
crcPwrOnRst : in sl := not RST_POLARITY_G;
50+
crcOut : out slv(31 downto 0); -- CRC output
51+
crcRem : out slv(31 downto 0); -- CRC interim remainder
5152
crcClk : in sl; -- system clock
5253
crcDataValid : in sl; -- indicate that new data arrived and CRC can be computed
5354
crcDataWidth : in slv(2 downto 0); -- indicate width in bytes minus 1, 0 - 1 byte, 1 - 2 bytes ... , 7 - 8 bytes
5455
crcIn : in slv((BYTE_WIDTH_G*8-1) downto 0); -- input data for CRC calculation
5556
crcInit : in slv(31 downto 0) := CRC_INIT_G; -- optional override of CRC_INIT_G
56-
crcReset : in sl); -- initializes CRC logic to crcInit
57+
crcReset : in sl); -- initializes CRC logic to crcInit
5758
end Crc32Parallel;
5859

5960
architecture rtl of Crc32Parallel is
@@ -188,10 +189,10 @@ begin
188189

189190
seq : process (crcClk, crcPwrOnRst) is
190191
begin
191-
if (RST_ASYNC_G and crcPwrOnRst = '1') then
192+
if (RST_ASYNC_G and crcPwrOnRst = RST_POLARITY_G) then
192193
r <= REG_INIT_C after TPD_G;
193-
elsif (rising_edge(crcClk)) then
194-
if (RST_ASYNC_G = false and crcPwrOnRst = '1') then
194+
elsif (rising_edge(crcClk)) then
195+
if (RST_ASYNC_G = false and crcPwrOnRst = RST_POLARITY_G) then
195196
r <= REG_INIT_C after TPD_G;
196197
else
197198
r <= rin after TPD_G;

‎base/general/rtl/Scrambler.vhd

+3-2
Original file line numberDiff line numberDiff line change
@@ -25,6 +25,7 @@ use surf.StdRtlPkg.all;
2525
entity Scrambler is
2626
generic (
2727
TPD_G : time := 1 ns;
28+
RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset
2829
RST_ASYNC_G : boolean := false;
2930
DIRECTION_G : string := "SCRAMBLER"; -- or DESCRAMBLER
3031
DATA_WIDTH_G : integer := 64;
@@ -129,7 +130,7 @@ begin
129130
inputReady <= v.inputReady;
130131

131132
-- Reset
132-
if (RST_ASYNC_G = false and rst = '1') then
133+
if (RST_ASYNC_G = false and rst = RST_POLARITY_G) then
133134
v := REG_INIT_C;
134135
end if;
135136

@@ -150,7 +151,7 @@ begin
150151

151152
seq : process (clk, rst) is
152153
begin
153-
if (RST_ASYNC_G and rst = '1') then
154+
if (RST_ASYNC_G and rst = RST_POLARITY_G) then
154155
r <= REG_INIT_C after TPD_G;
155156
elsif rising_edge(clk) then
156157
r <= rin after TPD_G;

‎base/sync/rtl/RstSync.vhd

+7-4
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,9 @@
44
-- Description: Synchronizes the trailing edge of an asynchronous reset to a
55
-- given clock.
66
-------------------------------------------------------------------------------
7+
-- Note: Using "std_logic" instead of "sl" for generics due to issues with
8+
-- SystemVerilog handling VHDL subtype on generics properly
9+
-------------------------------------------------------------------------------
710
-- This file is part of 'SLAC Firmware Standard Library'.
811
-- It is subject to the license terms in the LICENSE.txt file found in the
912
-- top-level directory of this distribution and at:
@@ -21,9 +24,9 @@ use surf.StdRtlPkg.all;
2124

2225
entity RstSync is
2326
generic (
24-
TPD_G : time := 1 ns; -- Simulation FF output delay
25-
IN_POLARITY_G : sl := '1'; -- 0 for active low rst, 1 for high
26-
OUT_POLARITY_G : sl := '1';
27+
TPD_G : time := 1 ns; -- Simulation FF output delay
28+
IN_POLARITY_G : std_logic := '1'; -- 0 for active low rst, 1 for high
29+
OUT_POLARITY_G : std_logic := '1';
2730
BYPASS_SYNC_G : boolean := false; -- Bypass Synchronizer module for synchronous data configuration
2831
RELEASE_DELAY_G : integer range 3 to positive'high := 3; -- Delay between deassertion of async and sync resets
2932
OUT_REG_RST_G : boolean := true); -- Apply async reset to final reg stage
@@ -57,7 +60,7 @@ begin
5760
dataOut => syncInt);
5861

5962
-- Final stage does not have async constraints applied, can be duplicated to ease timing
60-
OUT_REG : process (clk, asyncRst) is
63+
OUT_REG : process (asyncRst, clk) is
6164
begin
6265
if (asyncRst = IN_POLARITY_G and OUT_REG_RST_G) then
6366
syncRst <= OUT_POLARITY_G after TPD_G;

‎base/sync/rtl/SynchronizerFifo.vhd

+21-19
Original file line numberDiff line numberDiff line change
@@ -22,18 +22,19 @@ use surf.StdRtlPkg.all;
2222

2323
entity SynchronizerFifo is
2424
generic (
25-
TPD_G : time := 1 ns;
26-
RST_ASYNC_G : boolean := false;
27-
COMMON_CLK_G : boolean := false; -- Bypass FifoAsync module for synchronous data configuration
28-
MEMORY_TYPE_G : string := "distributed";
29-
SYNC_STAGES_G : integer range 3 to (2**24) := 3;
30-
PIPE_STAGES_G : natural range 0 to 16 := 0;
31-
DATA_WIDTH_G : integer range 1 to (2**24) := 16;
32-
ADDR_WIDTH_G : integer range 2 to 48 := 4;
33-
INIT_G : slv := "0");
25+
TPD_G : time := 1 ns;
26+
RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset
27+
RST_ASYNC_G : boolean := false;
28+
COMMON_CLK_G : boolean := false; -- Bypass FifoAsync module for synchronous data configuration
29+
MEMORY_TYPE_G : string := "distributed";
30+
SYNC_STAGES_G : integer range 3 to (2**24) := 3;
31+
PIPE_STAGES_G : natural range 0 to 16 := 0;
32+
DATA_WIDTH_G : integer range 1 to (2**24) := 16;
33+
ADDR_WIDTH_G : integer range 2 to 48 := 4;
34+
INIT_G : slv := "0");
3435
port (
3536
-- Asynchronous Reset
36-
rst : in sl := '0';
37+
rst : in sl := not RST_POLARITY_G;
3738
-- Write Ports (wr_clk domain)
3839
wr_clk : in sl;
3940
wr_en : in sl := '1';
@@ -58,15 +59,16 @@ begin
5859

5960
FifoAsync_1 : entity surf.FifoAsync
6061
generic map (
61-
TPD_G => TPD_G,
62-
RST_ASYNC_G => RST_ASYNC_G,
63-
MEMORY_TYPE_G => MEMORY_TYPE_G,
64-
FWFT_EN_G => true,
65-
SYNC_STAGES_G => SYNC_STAGES_G,
66-
PIPE_STAGES_G => PIPE_STAGES_G,
67-
DATA_WIDTH_G => DATA_WIDTH_G,
68-
ADDR_WIDTH_G => ADDR_WIDTH_G,
69-
INIT_G => INIT_C)
62+
TPD_G => TPD_G,
63+
RST_POLARITY_G => RST_POLARITY_G,
64+
RST_ASYNC_G => RST_ASYNC_G,
65+
MEMORY_TYPE_G => MEMORY_TYPE_G,
66+
FWFT_EN_G => true,
67+
SYNC_STAGES_G => SYNC_STAGES_G,
68+
PIPE_STAGES_G => PIPE_STAGES_G,
69+
DATA_WIDTH_G => DATA_WIDTH_G,
70+
ADDR_WIDTH_G => ADDR_WIDTH_G,
71+
INIT_G => INIT_C)
7072
port map (
7173
rst => rst,
7274
wr_clk => wr_clk,

0 commit comments

Comments
 (0)