diff --git a/lambdapdk/__init__.py b/lambdapdk/__init__.py
index b25d2fbf..5338540f 100644
--- a/lambdapdk/__init__.py
+++ b/lambdapdk/__init__.py
@@ -1,7 +1,7 @@
 import siliconcompiler.package as sc_package
 
 
-__version__ = "0.1.42"
+__version__ = "0.1.43"
 
 
 def register_data_source(chip):
diff --git a/lambdapdk/gf180/libs/gf180mcu_fd_sc_mcu7t5v0/apr/openroad/pdngen.tcl b/lambdapdk/gf180/libs/gf180mcu_fd_sc_mcu7t5v0/apr/openroad/pdngen.tcl
index a39a046c..877491c7 100644
--- a/lambdapdk/gf180/libs/gf180mcu_fd_sc_mcu7t5v0/apr/openroad/pdngen.tcl
+++ b/lambdapdk/gf180/libs/gf180mcu_fd_sc_mcu7t5v0/apr/openroad/pdngen.tcl
@@ -5,8 +5,8 @@ set_voltage_domain -name {CORE} -power {VDD} -ground {VSS}
 ####################################
 # standard cell grid
 ####################################
-define_pdn_grid -name {block} -voltage_domains {CORE}
-add_pdn_stripe -grid {block} -layer {Metal1} -width {0.900} -pitch {3.92} -offset {0} -followpins
+define_pdn_grid -name {grid} -voltage_domains {CORE}
+add_pdn_stripe -grid {grid} -layer {Metal1} -width {0.900} -pitch {3.92} -offset {0} -followpins
 
 set metal4_pitch [expr {([lindex [ord::get_core_area] 2] - [lindex [ord::get_core_area] 0]) / 2}]
 if {$metal4_pitch > 44.8} {
@@ -31,6 +31,6 @@ add_pdn_stripe -grid {grid} -layer {Metal4} -width {1.600} -pitch [snap_grid $me
     -offset [snap_grid [expr {$metal4_pitch / 4}]]
 add_pdn_stripe -grid {grid} -layer {Metal5} -width {1.600} -pitch [snap_grid $metal5_pitch] \
     -offset [snap_grid [expr {$metal5_pitch / 4}]]
-add_pdn_connect -grid {block} -layers {Metal1 Metal4} -max_columns {5} \
+add_pdn_connect -grid {grid} -layers {Metal1 Metal4} -max_columns {5} \
     -ongrid {Metal2 Metal3 Metal4}
-add_pdn_connect -grid {block} -layers {Metal4 Metal5}
+add_pdn_connect -grid {grid} -layers {Metal4 Metal5}
diff --git a/lambdapdk/gf180/libs/gf180mcu_fd_sc_mcu9t5v0/apr/openroad/pdngen.tcl b/lambdapdk/gf180/libs/gf180mcu_fd_sc_mcu9t5v0/apr/openroad/pdngen.tcl
index fda48493..aff74001 100644
--- a/lambdapdk/gf180/libs/gf180mcu_fd_sc_mcu9t5v0/apr/openroad/pdngen.tcl
+++ b/lambdapdk/gf180/libs/gf180mcu_fd_sc_mcu9t5v0/apr/openroad/pdngen.tcl
@@ -5,8 +5,8 @@ set_voltage_domain -name {CORE} -power {VDD} -ground {VSS}
 ####################################
 # standard cell grid
 ####################################
-define_pdn_grid -name {block} -voltage_domains {CORE}
-add_pdn_stripe -grid {block} -layer {Metal1} -width {0.900} -pitch {5.040} -offset {0} -followpins
+define_pdn_grid -name {grid} -voltage_domains {CORE}
+add_pdn_stripe -grid {grid} -layer {Metal1} -width {0.900} -pitch {5.040} -offset {0} -followpins
 
 set metal4_pitch [expr {([lindex [ord::get_core_area] 2] - [lindex [ord::get_core_area] 0]) / 2}]
 if {$metal4_pitch > 44.8} {
@@ -31,6 +31,6 @@ add_pdn_stripe -grid {grid} -layer {Metal4} -width {1.600} -pitch [snap_grid $me
     -offset [snap_grid [expr {$metal4_pitch / 4}]]
 add_pdn_stripe -grid {grid} -layer {Metal5} -width {1.600} -pitch [snap_grid $metal5_pitch] \
     -offset [snap_grid [expr {$metal5_pitch / 4}]]
-add_pdn_connect -grid {block} -layers {Metal1 Metal4} -max_columns {5} \
+add_pdn_connect -grid {grid} -layers {Metal1 Metal4} -max_columns {5} \
     -ongrid {Metal2 Metal3 Metal4}
-add_pdn_connect -grid {block} -layers {Metal4 Metal5}
+add_pdn_connect -grid {grid} -layers {Metal4 Metal5}