Can't map parts of signals in duh

[v-krvavac]

Is there a way to map parts of signals in duh? For example, we have a 32-bit interrupt signal in the PLDA RTL, and we currently have to break it into 32 1-bit signals in the RTL in order to be able to map it to the bus interface.

Example:
In json5 file:
portMaps: {
INT0: 'local_interrupt_out0',
INT1: 'local_interrupt_out1',
INT2: 'local_interrupt_out2',
INT3: 'local_interrupt_out3',
INT4: 'local_interrupt_out4',
......

Added code in RTL in order to support the above:

assign local_interrupt_out0 = local_interrupt_out[0];
assign local_interrupt_out1 = local_interrupt_out[1];
assign local_interrupt_out2 = local_interrupt_out[2];
assign local_interrupt_out3 = local_interrupt_out[3];
......