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A13_test_project.kicad_pro
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A13_test_project.kicad_pro
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{
"board": {
"design_settings": {
"defaults": {
"board_outline_line_width": 0.049999999999999996,
"copper_line_width": 0.19999999999999998,
"copper_text_italic": false,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"copper_text_upright": false,
"courtyard_line_width": 0.049999999999999996,
"dimension_precision": 4,
"dimension_units": 3,
"dimensions": {
"arrow_length": 1270000,
"extension_offset": 500000,
"keep_text_aligned": true,
"suppress_zeroes": false,
"text_position": 0,
"units_format": 1
},
"fab_line_width": 0.09999999999999999,
"fab_text_italic": false,
"fab_text_size_h": 1.0,
"fab_text_size_v": 1.0,
"fab_text_thickness": 0.15,
"fab_text_upright": false,
"other_line_width": 0.09999999999999999,
"other_text_italic": false,
"other_text_size_h": 1.0,
"other_text_size_v": 1.0,
"other_text_thickness": 0.15,
"other_text_upright": false,
"pads": {
"drill": 0.762,
"height": 1.524,
"width": 1.524
},
"silk_line_width": 0.09999999999999999,
"silk_text_italic": false,
"silk_text_size_h": 1.0,
"silk_text_size_v": 1.0,
"silk_text_thickness": 0.15,
"silk_text_upright": false,
"zones": {
"45_degree_only": false,
"min_clearance": 0.254
}
},
"diff_pair_dimensions": [
{
"gap": 0.0,
"via_gap": 0.0,
"width": 0.0
}
],
"drc_exclusions": [],
"meta": {
"filename": "board_design_settings.json",
"version": 2
},
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"copper_edge_clearance": "error",
"courtyards_overlap": "error",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"footprint_type_mismatch": "error",
"hole_clearance": "error",
"hole_near_hole": "error",
"invalid_outline": "error",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"missing_courtyard": "ignore",
"missing_footprint": "warning",
"net_conflict": "warning",
"npth_inside_courtyard": "ignore",
"padstack": "error",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_over_copper": "warning",
"silk_overlap": "ignore",
"skew_out_of_range": "error",
"through_hole_pad_without_hole": "error",
"too_many_vias": "error",
"track_dangling": "warning",
"track_width": "error",
"tracks_crossing": "error",
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zone_has_empty_net": "error",
"zones_intersect": "error"
},
"rule_severitieslegacy_courtyards_overlap": true,
"rule_severitieslegacy_no_courtyard_defined": false,
"rules": {
"allow_blind_buried_vias": false,
"allow_microvias": false,
"max_error": 0.005,
"min_clearance": 0.0,
"min_copper_edge_clearance": 0.024999999999999998,
"min_hole_clearance": 0.127,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.09999999999999999,
"min_microvia_drill": 0.09999999999999999,
"min_silk_clearance": 0.0,
"min_through_hole_diameter": 0.09999999999999999,
"min_track_width": 0.09999999999999999,
"min_via_annular_width": 0.049999999999999996,
"min_via_diameter": 0.39999999999999997,
"use_height_for_length_calcs": true
},
"track_widths": [
0.0
],
"via_dimensions": [
{
"diameter": 0.0,
"drill": 0.0
}
],
"zones_allow_external_fillets": false,
"zones_use_no_outline": true
},
"layer_presets": []
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"erc": {
"erc_exclusions": [],
"meta": {
"version": 0
},
"pin_map": [
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],
[
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]
],
"rule_severities": {
"bus_definition_conflict": "error",
"bus_entry_needed": "error",
"bus_label_syntax": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
"duplicate_sheet_names": "error",
"extra_units": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"lib_symbol_issues": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
"no_connect_dangling": "warning",
"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "warning",
"power_pin_not_driven": "error",
"similar_labels": "warning",
"unannotated": "error",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
"wire_dangling": "error"
}
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "A13_test_project.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 12.0,
"clearance": 0.125,
"diff_pair_gap": 0.1,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.1,
"line_style": 0,
"microvia_diameter": 0.2,
"microvia_drill": 0.1,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.127,
"via_diameter": 0.4,
"via_drill": 0.2,
"wire_width": 6.0
},
{
"bus_width": 12.0,
"clearance": 0.125,
"diff_pair_gap": 0.1,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.1,
"line_style": 0,
"microvia_diameter": 0.2,
"microvia_drill": 0.1,
"name": "DDR3",
"nets": [
"DDR3_A0",
"DDR3_A1",
"DDR3_A10",
"DDR3_A11",
"DDR3_A12",
"DDR3_A13",
"DDR3_A14",
"DDR3_A2",
"DDR3_A3",
"DDR3_A4",
"DDR3_A5",
"DDR3_A6",
"DDR3_A7",
"DDR3_A8",
"DDR3_A9",
"DDR3_BA0",
"DDR3_BA1",
"DDR3_BA2",
"DDR3_CK",
"DDR3_CKE",
"DDR3_D0",
"DDR3_D1",
"DDR3_D10",
"DDR3_D11",
"DDR3_D12",
"DDR3_D13",
"DDR3_D14",
"DDR3_D15",
"DDR3_D2",
"DDR3_D3",
"DDR3_D4",
"DDR3_D5",
"DDR3_D6",
"DDR3_D7",
"DDR3_D8",
"DDR3_D9",
"DDR3_LDM",
"DDR3_LDQS",
"DDR3_ODT",
"DDR3_SVREF",
"DDR3_UDM",
"DDR3_UDQS",
"DDR3_~{CAS}",
"DDR3_~{CK}",
"DDR3_~{LDQS}",
"DDR3_~{RAS}",
"DDR3_~{RESET}",
"DDR3_~{UDQS}",
"DDR3_~{WE}"
],
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.127,
"via_diameter": 0.4,
"via_drill": 0.2,
"wire_width": 6.0
},
{
"bus_width": 12.0,
"clearance": 0.125,
"diff_pair_gap": 0.1,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.1,
"line_style": 0,
"microvia_diameter": 0.2,
"microvia_drill": 0.1,
"name": "Power",
"nets": [
"+1V2",
"+1V5",
"+3V0",
"+3V3",
"+5V",
"GND"
],
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.2,
"via_diameter": 0.4,
"via_drill": 0.2,
"wire_width": 6.0
},
{
"bus_width": 12.0,
"clearance": 0.125,
"diff_pair_gap": 0.1,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.1,
"line_style": 0,
"microvia_diameter": 0.2,
"microvia_drill": 0.1,
"name": "USB",
"nets": [
"HOST_UDM",
"HOST_UDP"
],
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.2,
"via_diameter": 0.5,
"via_drill": 0.2,
"wire_width": 6.0
}
],
"meta": {
"version": 2
},
"net_colors": null
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "A13_test_project.net",
"specctra_dsn": "",
"step": "",
"vrml": ""
},
"page_layout_descr_file": ""
},
"schematic": {
"annotate_start_num": 0,
"drawing": {
"default_line_thickness": 6.0,
"default_text_size": 50.0,
"field_names": [],
"intersheets_ref_own_page": false,
"intersheets_ref_prefix": "",
"intersheets_ref_short": false,
"intersheets_ref_show": false,
"intersheets_ref_suffix": "",
"junction_size_choice": 3,
"label_size_ratio": 0.25,
"pin_symbol_size": 25.0,
"text_offset_ratio": 0.08
},
"legacy_lib_dir": "",
"legacy_lib_list": [],
"meta": {
"version": 1
},
"net_format_name": "Pcbnew",
"ngspice": {
"fix_include_paths": true,
"fix_passive_vals": false,
"meta": {
"version": 0
},
"model_mode": 0,
"workbook_filename": ""
},
"page_layout_descr_file": "",
"plot_directory": "",
"spice_adjust_passive_values": false,
"spice_external_command": "spice \"%I\"",
"subpart_first_id": 65,
"subpart_id_separator": 0
},
"sheets": [
[
"7d0dab95-9e7a-486e-a1d7-fc48860fd57d",
""
]
],
"text_variables": {}
}