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Kernel fails to boot on Nitrogen6_SoloX (or missing setup instructions) #631

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kent-mcleod opened this issue Oct 25, 2021 · 2 comments
Closed

Kernel fails to boot on Nitrogen6_SoloX (or missing setup instructions) #631

kent-mcleod opened this issue Oct 25, 2021 · 2 comments

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@kent-mcleod
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The default sel4test image for this platform produces an elfloader ELF file inside ./images. Trying to boot this file on a new board doesn't seem to work, there are no other instructions for how to run this platform:

U-Boot 2018.07-36618-g616d48151d (Oct 08 2020 - 10:15:22 -0700), Build: jenkins-uboot_v2018.07-240

CPU:   Freescale i.MX6SX rev1.3 at 792 MHz
Reset cause: WDOG
Board: nitrogen6sx
I2C:   ready
DRAM:  1 GiB
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
Loading Environment from SPI Flash...
SF: Detected gd25q16c with page size 256 Bytes, erase size 4 KiB, total 2 MiB
*** Warning - bad CRC, using default environment

Failed (-5)
Display: lcd:1280x720M@60 (1280x720)
In:    serial
Out:   serial
Err:   serial
Net:   AR8035 at 4
AR8035 at 5
FEC0 [PRIME], FEC1, usb_ether
Hit any key to stop autoboot:  0 
=> fastboot -l 0x82000000 0
Starting download of 5314952 bytes
........................................
downloading of 5314952 bytes finished
=> bootelf 0x82000000
CACHE: Misaligned operation at range [80848000, 80848034]
CACHE: Misaligned operation at range [80849000, 80853d38]
CACHE: Misaligned operation at range [80853d38, 80854c87]
CACHE: Misaligned operation at range [80854c88, 80854c90]
CACHE: Misaligned operation at range [80858000, 8086504c]
CACHE: Misaligned operation at range [80865050, 80d2a850]
CACHE: Misaligned operation at range [80d3a850, 80d3a888]
CACHE: Misaligned operation at range [80d3a888, 80d3a8b8]
## Starting application at 0x80848000 ...

ELF-loader started on CPU: ARM Ltd. Cortex-A9 r2p10
  paddr=[80848000..80d3a8b7]
No DTB passed in from boot loader.
Looking for DTB in CPIO archive...found at 809729e8.
Loaded DTB from 809729e8.
   paddr=[80040000..80043fff]
ELF-loading image 'kernel' to 80000000
  paddr=[80000000..8003ffff]
  vaddr=[e0000000..e003ffff]
  virt_entry=e0000000
ELF-loading image 'sel4test-driver' to 80044000
  paddr=[80044000..80449fff]
  vaddr=[10000..415fff]
  virt_entry=1e4c0
Enabling MMU and paging
abort() called.

Built with: ../init-build.sh -DPLATFORM=nitrogen6sx && ninja
@kent-mcleod
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The same also occurs with bootelf via tftp:

=> tftp 0x82000000 10.0.121.19:sel4test-driver-image-arm-imx6   
Using FEC0 device
TFTP from server 10.0.121.19; our IP address is 10.0.121.29
Filename 'sel4test-driver-image-arm-imx6'.
Load address: 0x82000000
Loading: #################################################################
	 #################################################################
	 #################################################################
	 #################################################################
	 #################################################################
	 ######################################
	 21.5 MiB/s
done
Bytes transferred = 5314952 (511988 hex)
=> bootelf 0x82000000
CACHE: Misaligned operation at range [80848000, 80848034]
CACHE: Misaligned operation at range [80849000, 80853d38]
CACHE: Misaligned operation at range [80853d38, 80854c87]
CACHE: Misaligned operation at range [80854c88, 80854c90]
CACHE: Misaligned operation at range [80858000, 8086504c]
CACHE: Misaligned operation at range [80865050, 80d2a850]
CACHE: Misaligned operation at range [80d3a850, 80d3a888]
CACHE: Misaligned operation at range [80d3a888, 80d3a8b8]
## Starting application at 0x80848000 ...

ELF-loader started on CPU: ARM Ltd. Cortex-A9 r2p10
  paddr=[80848000..80d3a8b7]
No DTB passed in from boot loader.
Looking for DTB in CPIO archive...found at 809729e8.
Loaded DTB from 809729e8.
   paddr=[80040000..80043fff]
ELF-loading image 'kernel' to 80000000
  paddr=[80000000..8003ffff]
  vaddr=[e0000000..e003ffff]
  virt_entry=e0000000
ELF-loading image 'sel4test-driver' to 80044000
  paddr=[80044000..80449fff]
  vaddr=[10000..415fff]
  virt_entry=1e4c0
Enabling MMU and paging
abort() called.

The same thing happens when ElfloaderImage=binary:

=> tftp 0x80849000 10.0.121.19:sel4test-driver-image-arm-imx6
Using FEC0 device
TFTP from server 10.0.121.19; our IP address is 10.0.121.29
Filename 'sel4test-driver-image-arm-imx6'.
Load address: 0x80849000
Loading: #################################################################
	 #################################################################
	 #################################################################
	 #################################################################
	 #################################################################
	 ########################
	 21.4 MiB/s
done
Bytes transferred = 5120696 (4e22b8 hex)
=> go 0x80849000
## Starting application at 0x80849000 ...

ELF-loader started on CPU: ARM Ltd. Cortex-A9 r2p10
  paddr=[80849000..80d2b2b7]
No DTB passed in from boot loader.
Looking for DTB in CPIO archive...found at 8095e25c.
Loaded DTB from 8095e25c.
   paddr=[80040000..80043fff]
ELF-loading image 'kernel' to 80000000
  paddr=[80000000..8003ffff]
  vaddr=[e0000000..e003ffff]
  virt_entry=e0000000
ELF-loading image 'sel4test-driver' to 80044000
  paddr=[80044000..8044afff]
  vaddr=[10000..416fff]
  virt_entry=1e3d0
Enabling MMU and paging
abort() called.

bootefi just hangs (when ElfloaderImage="efi"):

=> tftpboot 10.0.121.19:sel4test-driver-image-arm-imx6
Using FEC0 device
TFTP from server 10.0.121.19; our IP address is 10.0.121.29
Filename 'sel4test-driver-image-arm-imx6'.
Load address: 0x82000000
Loading: #################################################################
	 #################################################################
	 #################################################################
	 #################################################################
	 #################################################################
	 #####################
	 5.8 MiB/s
done
Bytes transferred = 5066940 (4d50bc hex)
=> bootefi 0x82000000
WARNING: booting without device tree
## Starting EFI application at 82000000 ...

ELF-loader started on CPU: ARM Ltd. Cortex-A9 r2p10
  paddr=[bde6d000..be342fff]
No DTB passed in from boot loader.
Looking for DTB in CPIO archive...found at bdf764a4.
Loaded DTB from bdf764a4.
   paddr=[80040000..80043fff]
ELF-loading image 'kernel' to 80000000
  paddr=[80000000..8003ffff]
  vaddr=[e0000000..e003ffff]
  virt_entry=e0000000
ELF-loading image 'sel4test-driver' to 80044000
  paddr=[80044000..8044afff]
  vaddr=[10000..416fff]
  virt_entry=1e3d0
Enabling MMU and paging

bootm seems to be the only config that works (ElfloaderImage="uimage"):

=> tftp sel4test-driver-image-arm-imx6
Using FEC0 device
TFTP from server 10.0.121.19; our IP address is 10.0.121.29
Filename 'sel4test-driver-image-arm-imx6'.
Load address: 0x82000000
Loading: #################################################################
	 #################################################################
	 #################################################################
	 #################################################################
	 #################################################################
	 ########################
	 21.4 MiB/s
done
Bytes transferred = 5120760 (4e22f8 hex)
=> bootm
## Booting kernel from Legacy Image at 82000000 ...
   Image Name:   
   Image Type:   ARM Linux Kernel Image (uncompressed)
   Data Size:    5120696 Bytes = 4.9 MiB
   Load Address: 80849000
   Entry Point:  80849000
   Verifying Checksum ... OK
   Loading Kernel Image ... OK

Starting kernel ...


ELF-loader started on CPU: ARM Ltd. Cortex-A9 r2p10
  paddr=[80849000..80d2b2b7]
No DTB passed in from boot loader.
Looking for DTB in CPIO archive...found at 8095e224.
Loaded DTB from 8095e224.
   paddr=[80040000..80043fff]
ELF-loading image 'kernel' to 80000000
  paddr=[80000000..8003ffff]
  vaddr=[e0000000..e003ffff]
  virt_entry=e0000000
ELF-loading image 'sel4test-driver' to 80044000
  paddr=[80044000..8044afff]
  vaddr=[10000..416fff]
  virt_entry=1e3d0
Enabling MMU and paging
Jumping to kernel-image entry point...

DIDRv: 3, armv 70, coproc baseline only? no.
CPU is in secure mode. Enabling debugging in secure user mode.
Bootstrapping kernel
available phys memory regions: 1
  [80000000..c0000000]
reserved virt address space regions: 4
  [e0000000..e0040000]
  [e0040000..e0044000]
  [e0044000..e044b000]
  [ff000000..ff100000]
Booting all finished, dropped to user space
Node 0 of 1
IOPT levels:     0
IPC buffer:      0x417000
Empty slots:     [1129 --> 8192)
sharedFrames:    [0 --> 0)
userImageFrames: [23 --> 1054)
userImagePaging: [14 --> 19)
untypeds:        [1054 --> 1129)
Initial thread domain: 0
Initial thread cnode size: 13
List of untypeds
------------------
Paddr    | Size   | Device
0 | 23 | 1
0x800000 | 21 | 1
0xa03000 | 12 | 1
0xa04000 | 14 | 1

@kent-mcleod
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Issue seems to be due to the default uboot loading the elfloader with caches enabled and dirty. The elfloader doesn't currently have a PL310 L2 Cache controller driver that it can use to flush the cache before disabling it. So when it tries to enable the MMU the return address stored on the stack gets corrupted and when the function for enabling the mmu returns the processor jumps to a bad address and later aborts.

An easy way to use these other uboot methods is to first call dcache off which will flush to Ram and then turn off data and unified caching in the SCTLR. I'll create an issue in the elfloader repository about the missing L2C flushing support.

@kent-mcleod kent-mcleod mentioned this issue Nov 12, 2021
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