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Some way of blocking simp from unifying schematics #730

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Xaphiosis opened this issue Mar 7, 2024 · 1 comment
Open

Some way of blocking simp from unifying schematics #730

Xaphiosis opened this issue Mar 7, 2024 · 1 comment
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proof engineering nicer, shorter, more maintainable etc proofs proof tools convenience, automation, productivity tools

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@Xaphiosis
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As seen in #729 if wp or some other tool gets you into a bad situation, e.g. schematic assumption, simp will happily unify that with False which will result in very bad outcomes in wp proofs.
clarsimp of course prevents this problem, but it involves clarify and so blows up ∃val. x = Some val to introduce a free variable that a precondition schematic doesn't rely on, creating the problem for wp and simp to make worse. So in these cases we need simp, but without having it instantiate schematics.

If we have a safer wp, a safer vcg and a safer simp, we have some weaponry in stabilising some of the more horrid ccorres proofs like the fastpath ones.

@Xaphiosis Xaphiosis added proof engineering nicer, shorter, more maintainable etc proofs proof tools convenience, automation, productivity tools labels Mar 7, 2024
@lsf37
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lsf37 commented Apr 19, 2024

This one I have slightly less hope for -- it's likely that we'd have to go deep into the guts of simp to prevent it from instantiating schematics and changing fundamental simp behaviour is going to be very subtle.

That said, one avenue of exploration could be to look at how clarsimp prevents simp from instantiating schematics and see if that could be extracted somehow into a new method.

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Labels
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