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top_module_map.mrp
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top_module_map.mrp
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Release 14.7 Map P.20131013 (nt64)
Xilinx Mapping Report File for Design 'top_module'
Design Information
------------------
Command Line : map -intstyle ise -p xc3s400-pq208-4 -cm area -ir off -pr off
-c 100 -o top_module_map.ncd top_module.ngd top_module.pcf
Target Device : xc3s400
Target Package : pq208
Target Speed : -4
Mapper Version : spartan3 -- $Revision: 1.55 $
Mapped Date : Sat Oct 20 10:25:19 2018
Design Summary
--------------
Number of errors: 0
Number of warnings: 0
Logic Utilization:
Number of Slice Flip Flops: 112 out of 7,168 1%
Number of 4 input LUTs: 62 out of 7,168 1%
Logic Distribution:
Number of occupied Slices: 98 out of 3,584 2%
Number of Slices containing only related logic: 98 out of 98 100%
Number of Slices containing unrelated logic: 0 out of 98 0%
*See NOTES below for an explanation of the effects of unrelated logic.
Total Number of 4 input LUTs: 180 out of 7,168 2%
Number used as logic: 62
Number used as a route-thru: 118
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
Number of bonded IOBs: 6 out of 141 4%
Number of BUFGMUXs: 3 out of 8 37%
Number of DCMs: 1 out of 4 25%
Average Fanout of Non-Clock Nets: 2.38
Peak Memory Usage: 4408 MB
Total REAL time to MAP completion: 1 secs
Total CPU time to MAP completion: 1 secs
NOTES:
Related logic is defined as being logic that shares connectivity - e.g. two
LUTs are "related" if they share common inputs. When assembling slices,
Map gives priority to combine logic that is related. Doing so results in
the best timing performance.
Unrelated logic shares no connectivity. Map will only begin packing
unrelated logic into a slice once 99% of the slices are occupied through
related logic packing.
Note that once logic distribution reaches the 99% level through related
logic packing, this does not mean the device is completely utilized.
Unrelated logic packing will then begin, continuing until all usable LUTs
and FFs are occupied. Depending on your timing budget, increased levels of
unrelated logic packing may adversely affect the overall timing performance
of your design.
Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Timing Report
Section 11 - Configuration String Information
Section 12 - Control Set Information
Section 13 - Utilization by Hierarchy
Section 1 - Errors
------------------
Section 2 - Warnings
--------------------
Section 3 - Informational
-------------------------
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
rate limited output drivers. The delay on speed critical single ended outputs
can be dramatically reduced by designating them as fast outputs.
INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance
with the CLKFX and CLKFX180 outputs of the DCM comp Inst_my_dcm/DCM_INST,
consult the device Interactive Data Sheet.
Section 4 - Removed Logic Summary
---------------------------------
2 block(s) optimized away
Section 5 - Removed Logic
-------------------------
Optimized Block(s):
TYPE BLOCK
GND XST_GND
VCC XST_VCC
To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.
Section 6 - IOB Properties
--------------------------
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB |
| | | | | Term | Strength | Rate | | | Delay |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| i_CLK | IOB | INPUT | LVCMOS25 | | | | | | |
| i_RST | IOB | INPUT | LVCMOS25 | | | | | PULLDOWN | |
| o_LED<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| o_LED<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| o_LED<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| o_LED<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
Section 7 - RPMs
----------------
Section 8 - Guide Report
------------------------
Guide not run on this design.
Section 9 - Area Group and Partition Summary
--------------------------------------------
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Area Group Information
----------------------
No area groups were found in this design.
----------------------
Section 10 - Timing Report
--------------------------
This design was not run using timing mode.
Section 11 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings
Section 12 - Control Set Information
------------------------------------
No control set information for this architecture.
Section 13 - Utilization by Hierarchy
-------------------------------------
Use the "-detail" map option to print out the Utilization by Hierarchy section.