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top_module.twr
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top_module.twr
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--------------------------------------------------------------------------------
Release 14.7 Trace (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
D:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 4
-n 3 -fastpaths -xml top_module.twx top_module.ncd -o top_module.twr
top_module.pcf -ucf FPGA.ucf -ucf LED.ucf
Design file: top_module.ncd
Physical constraint file: top_module.pcf
Device,package,speed: xc3s400,pq208,-4 (PRODUCTION 1.39 2013-10-13)
Report level: verbose report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
a 50 Ohm transmission line loading model. For the details of this model,
and for more information on accounting for different loading conditions,
please see the device datasheet.
INFO:Timing:3390 - This architecture does not support a default System Jitter
value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock
Uncertainty calculation.
INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and
'Phase Error' calculations, these terms will be zero in the Clock
Uncertainty calculation. Please make appropriate modification to
SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase
Error.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Clock i_CLK to Pad
------------+------------+------------------+--------+
| clk (edge) | | Clock |
Destination | to PAD |Internal Clock(s) | Phase |
------------+------------+------------------+--------+
o_LED<0> | 8.875(R)|clk0 | 0.000|
o_LED<1> | 9.127(R)|clk20 | 0.000|
o_LED<2> | 8.335(R)|clk20 | 0.000|
o_LED<3> | 9.200(R)|clk65 | 0.000|
------------+------------+------------------+--------+
Clock to Setup on destination clock i_CLK
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
i_CLK | 6.050| | | |
---------------+---------+---------+---------+---------+
Analysis completed Sat Oct 20 10:25:32 2018
--------------------------------------------------------------------------------
Trace Settings:
-------------------------
Trace Settings
Peak Memory Usage: 4490 MB