-
Notifications
You must be signed in to change notification settings - Fork 0
/
top_module.cmd_log
59 lines (59 loc) · 6.3 KB
/
top_module.cmd_log
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
xst -intstyle ise -ifn "D:/books/darsi/7/az_cad/proj/main/top_module.xst" -ofn "D:/books/darsi/7/az_cad/proj/main/top_module.syr"
xst -intstyle ise -ifn "D:/books/darsi/7/az_cad/proj/main/top_module.xst" -ofn "D:/books/darsi/7/az_cad/proj/main/top_module.syr"
xst -intstyle ise -ifn "D:/books/darsi/7/az_cad/proj/main/top_module.xst" -ofn "D:/books/darsi/7/az_cad/proj/main/top_module.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc3s400-pq208-4 top_module.ngc top_module.ngd
map -intstyle ise -p xc3s400-pq208-4 -cm area -ir off -pr off -c 100 -o top_module_map.ncd top_module.ngd top_module.pcf
par -w -intstyle ise -ol high -t 1 top_module_map.ncd top_module.ncd top_module.pcf
trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml top_module.twx top_module.ncd -o top_module.twr top_module.pcf
bitgen -intstyle ise -f top_module.ut top_module.ncd
vhdtdtfi -prj main -o D:/books/darsi/7/az_cad/proj/main/top_module.vhi -module top_module -template D:/Xilinx/14.7/ISE_DS/ISE//data/vhdlinst.tft -deleteonerror -lib work my_dcm.vhd -lib work counter.vhd -lib work top_module.vhd
xst -intstyle ise -ifn "D:/books/darsi/7/az_cad/proj/main/top_module.xst" -ofn "D:/books/darsi/7/az_cad/proj/main/top_module.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc3s400-pq208-4 top_module.ngc top_module.ngd
map -intstyle ise -p xc3s400-pq208-4 -cm area -ir off -pr off -c 100 -o top_module_map.ncd top_module.ngd top_module.pcf
par -w -intstyle ise -ol high -t 1 top_module_map.ncd top_module.ncd top_module.pcf
trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml top_module.twx top_module.ncd -o top_module.twr top_module.pcf
bitgen -intstyle ise -f top_module.ut top_module.ncd
xst -intstyle ise -ifn "D:/books/darsi/7/az_cad/proj/main/top_module.xst" -ofn "D:/books/darsi/7/az_cad/proj/main/top_module.syr"
xst -intstyle ise -ifn "D:/books/darsi/7/az_cad/proj/main/top_module.xst" -ofn "D:/books/darsi/7/az_cad/proj/main/top_module.syr"
xst -intstyle ise -ifn "D:/books/darsi/7/az_cad/proj/main/top_module.xst" -ofn "D:/books/darsi/7/az_cad/proj/main/top_module.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc3s400-pq208-4 top_module.ngc top_module.ngd
map -intstyle ise -p xc3s400-pq208-4 -cm area -ir off -pr off -c 100 -o top_module_map.ncd top_module.ngd top_module.pcf
par -w -intstyle ise -ol high -t 1 top_module_map.ncd top_module.ncd top_module.pcf
trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml top_module.twx top_module.ncd -o top_module.twr top_module.pcf
bitgen -intstyle ise -f top_module.ut top_module.ncd
xst -intstyle ise -ifn "D:/books/darsi/7/az_cad/proj/main/top_module.xst" -ofn "D:/books/darsi/7/az_cad/proj/main/top_module.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc3s400-pq208-4 top_module.ngc top_module.ngd
map -intstyle ise -p xc3s400-pq208-4 -cm area -ir off -pr off -c 100 -o top_module_map.ncd top_module.ngd top_module.pcf
par -w -intstyle ise -ol high -t 1 top_module_map.ncd top_module.ncd top_module.pcf
trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml top_module.twx top_module.ncd -o top_module.twr top_module.pcf
bitgen -intstyle ise -f top_module.ut top_module.ncd
xst -intstyle ise -ifn "D:/books/darsi/7/az_cad/proj/main/top_module.xst" -ofn "D:/books/darsi/7/az_cad/proj/main/top_module.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc FPGA.ucf -uc LED.ucf -p xc3s400-pq208-4 top_module.ngc top_module.ngd
map -intstyle ise -p xc3s400-pq208-4 -cm area -ir off -pr off -c 100 -o top_module_map.ncd top_module.ngd top_module.pcf
par -w -intstyle ise -ol high -t 1 top_module_map.ncd top_module.ncd top_module.pcf
trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml top_module.twx top_module.ncd -o top_module.twr top_module.pcf -ucf FPGA.ucf -ucf LED.ucf
bitgen -intstyle ise -f top_module.ut top_module.ncd
xst -intstyle ise -ifn "D:/books/darsi/7/az_cad/proj/main/top_module.xst" -ofn "D:/books/darsi/7/az_cad/proj/main/top_module.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc FPGA.ucf -uc LED.ucf -p xc3s400-pq208-4 top_module.ngc top_module.ngd
map -intstyle ise -p xc3s400-pq208-4 -cm area -ir off -pr off -c 100 -o top_module_map.ncd top_module.ngd top_module.pcf
par -w -intstyle ise -ol high -t 1 top_module_map.ncd top_module.ncd top_module.pcf
trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml top_module.twx top_module.ncd -o top_module.twr top_module.pcf -ucf FPGA.ucf -ucf LED.ucf
bitgen -intstyle ise -f top_module.ut top_module.ncd
xst -intstyle ise -ifn "D:/books/darsi/7/az_cad/proj/main/top_module.xst" -ofn "D:/books/darsi/7/az_cad/proj/main/top_module.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc FPGA.ucf -uc LED.ucf -p xc3s400-pq208-4 top_module.ngc top_module.ngd
map -intstyle ise -p xc3s400-pq208-4 -cm area -ir off -pr off -c 100 -o top_module_map.ncd top_module.ngd top_module.pcf
par -w -intstyle ise -ol high -t 1 top_module_map.ncd top_module.ncd top_module.pcf
trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml top_module.twx top_module.ncd -o top_module.twr top_module.pcf -ucf FPGA.ucf -ucf LED.ucf
bitgen -intstyle ise -f top_module.ut top_module.ncd
xst -intstyle ise -ifn "D:/books/darsi/7/az_cad/proj/main/top_module.xst" -ofn "D:/books/darsi/7/az_cad/proj/main/top_module.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc FPGA.ucf -uc LED.ucf -p xc3s400-pq208-4 top_module.ngc top_module.ngd
map -intstyle ise -p xc3s400-pq208-4 -cm area -ir off -pr off -c 100 -o top_module_map.ncd top_module.ngd top_module.pcf
par -w -intstyle ise -ol high -t 1 top_module_map.ncd top_module.ncd top_module.pcf
trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml top_module.twx top_module.ncd -o top_module.twr top_module.pcf -ucf FPGA.ucf -ucf LED.ucf
bitgen -intstyle ise -f top_module.ut top_module.ncd
xst -intstyle ise -ifn "D:/books/darsi/7/az_cad/proj/main/top_module.xst" -ofn "D:/books/darsi/7/az_cad/proj/main/top_module.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc FPGA.ucf -uc LED.ucf -p xc3s400-pq208-4 top_module.ngc top_module.ngd
map -intstyle ise -p xc3s400-pq208-4 -cm area -ir off -pr off -c 100 -o top_module_map.ncd top_module.ngd top_module.pcf
par -w -intstyle ise -ol high -t 1 top_module_map.ncd top_module.ncd top_module.pcf
trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml top_module.twx top_module.ncd -o top_module.twr top_module.pcf -ucf FPGA.ucf -ucf LED.ucf
bitgen -intstyle ise -f top_module.ut top_module.ncd