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fuse.log
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fuse.log
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Running: D:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\fuse.exe -intstyle ise -incremental -o D:/books/darsi/7/az_cad/proj/main/top_module_tb_isim_beh.exe -prj D:/books/darsi/7/az_cad/proj/main/top_module_tb_beh.prj work.top_module_tb
ISim P.20131013 (signature 0x7708f090)
Number of CPUs detected in this system: 4
Turning on mult-threading, number of parallel sub-compilation jobs: 8
Determining compilation order of HDL files
Parsing VHDL file "D:/books/darsi/7/az_cad/proj/main/my_dcm.vhd" into library work
Parsing VHDL file "D:/books/darsi/7/az_cad/proj/main/counter.vhd" into library work
Parsing VHDL file "D:/books/darsi/7/az_cad/proj/main/top_module.vhd" into library work
Parsing VHDL file "D:/books/darsi/7/az_cad/proj/main/top_module_tb.vhd" into library work
Starting static elaboration
Completed static elaboration
Compiling package standard
Compiling package std_logic_1164
Compiling package numeric_std
Compiling package vcomponents
Compiling package textio
Compiling package vital_timing
Compiling package vital_primitives
Compiling package vpkg
Compiling architecture bufg_v of entity BUFG [bufg_default]
Compiling architecture ibufg_v of entity IBUFG [\IBUFG("DONT_CARE","0",true,"DEF...]
Compiling architecture dcm_clock_divide_by_2_v of entity dcm_clock_divide_by_2 [dcm_clock_divide_by_2_default]
Compiling architecture dcm_maximum_period_check_v of entity dcm_maximum_period_check [\dcm_maximum_period_check("CLKIN...]
Compiling architecture dcm_maximum_period_check_v of entity dcm_maximum_period_check [\dcm_maximum_period_check("PSCLK...]
Compiling architecture dcm_clock_lost_v of entity dcm_clock_lost [dcm_clock_lost_default]
Compiling architecture dcm_v of entity DCM [\DCM(2.0,8,13,false,25.0,"NONE",...]
Compiling architecture behavioral of entity my_dcm [my_dcm_default]
Compiling architecture behavioral of entity counter [\counter(400)\]
Compiling architecture behavioral of entity counter [\counter(200)\]
Compiling architecture behavioral of entity counter [\counter(100)\]
Compiling architecture behavioral of entity counter [\counter(50)\]
Compiling architecture behavioral of entity top_module [top_module_default]
Compiling architecture behavior of entity top_module_tb
Time Resolution for simulation is 1ps.
Waiting for 14 sub-compilation(s) to finish...
Compiled 35 VHDL Units
Built simulation executable D:/books/darsi/7/az_cad/proj/main/top_module_tb_isim_beh.exe
Fuse Memory Usage: 58776 KB
Fuse CPU Usage: 780 ms