From 41a6ff30214f6616c87831f9eafc0d3bd0b3779f Mon Sep 17 00:00:00 2001 From: "Sergey \"Shnatsel\" Davidoff" Date: Sun, 19 Jul 2026 20:23:42 +0100 Subject: [PATCH 01/10] Optimize swizzle_dyn for double the native vector width on SSE4.2, AVX2 and WASM --- crates/core_simd/src/swizzle_dyn.rs | 60 +++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/crates/core_simd/src/swizzle_dyn.rs b/crates/core_simd/src/swizzle_dyn.rs index 95fe086a4b4ab..30e6d18451e6c 100644 --- a/crates/core_simd/src/swizzle_dyn.rs +++ b/crates/core_simd/src/swizzle_dyn.rs @@ -41,6 +41,8 @@ impl Simd { 16 => transize(x86::_mm_shuffle_epi8, self, zeroing_idxs(idxs)), #[cfg(target_feature = "simd128")] 16 => transize(wasm::i8x16_swizzle, self, idxs), + #[cfg(target_feature = "simd128")] + 32 => transize(swizzle_dyn_split::<32, 16>, self, idxs), #[cfg(all( target_arch = "arm", target_feature = "v7", @@ -64,9 +66,17 @@ impl Simd { }; transize(swizzler, self, idxs) } + #[cfg(all( + target_feature = "ssse3", + not(target_feature = "avx2"), + not(target_feature = "avx512vbmi") + ))] + 32 => transize(swizzle_dyn_split::<32, 16>, self, idxs), #[cfg(all(target_arch = "loongarch64", target_feature = "lasx"))] 32 => transize(loong64_lasx_swizzle, self, idxs), // Notable absence: avx512bw pshufb shuffle + #[cfg(all(target_feature = "avx2", not(target_feature = "avx512vbmi")))] + 64 => transize(swizzle_dyn_split::<64, 32>, self, idxs), #[cfg(all(target_feature = "avx512vl", target_feature = "avx512vbmi"))] 64 => { // Unlike vpshufb, vpermb doesn't zero out values in the result based on the index high bit @@ -93,6 +103,56 @@ impl Simd { } } +#[cfg(any( + target_feature = "simd128", + all( + target_feature = "ssse3", + not(target_feature = "avx2"), + not(target_feature = "avx512vbmi") + ), + all(target_feature = "avx2", not(target_feature = "avx512vbmi")) +))] +/// Implements an arbitrary shuffle over double the native vector width +/// using 4 native-width shuffles +fn swizzle_dyn_split( + bytes: Simd, + idxs: Simd, +) -> Simd { + let table_low = bytes.extract::<0, HALF>(); + let table_high = bytes.extract::(); + let idxs_low = idxs.extract::<0, HALF>(); + let idxs_high = idxs.extract::(); + let table_high_offset = Simd::::splat(HALF as u8); + + let output_low_from_low = table_low.swizzle_dyn(idxs_low); + let output_low_from_high = table_high.swizzle_dyn(idxs_low - table_high_offset); + let output_low = output_low_from_low | output_low_from_high; + + let output_high_from_low = table_low.swizzle_dyn(idxs_high); + let output_high_from_high = table_high.swizzle_dyn(idxs_high - table_high_offset); + let output_high = output_high_from_low | output_high_from_high; + + // This is simply a concatenation of two native-sized vectors. + // The swizzle does nothing - it maps the elements right back where they already are. + // There doesn't seem to be a more direct way to do this as of this writing. + // TODO: simplify once a plain `concat` is available. + use crate::simd::Swizzle; + struct CombineHalves; + impl Swizzle for CombineHalves { + const INDEX: [usize; N] = const { + let mut index = [0; N]; + let mut i = 0; + while i < N { + index[i] = i; + i += 1; + } + index + }; + } + + CombineHalves::concat_swizzle(output_low, output_high) +} + /// armv7 neon supports swizzling `u8x16` by swizzling two u8x8 blocks /// with a u8x8x2 lookup table. /// From 363e3275c5966cd88ce66936936e715f503470e5 Mon Sep 17 00:00:00 2001 From: Folkert de Vries Date: Mon, 20 Jul 2026 00:12:00 +0200 Subject: [PATCH 02/10] use `main` instead of `master` for the `rust-lang/rust` branch name --- subtree-sync.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/subtree-sync.sh b/subtree-sync.sh index 18360077623b1..eab56bd03c65d 100755 --- a/subtree-sync.sh +++ b/subtree-sync.sh @@ -12,8 +12,8 @@ if [ "$(git rev-parse --show-prefix)" != "" ]; then exit 1 fi -if [ "$(git rev-parse HEAD)" != "$(git rev-parse origin/master)" ]; then - echo "$(pwd) is not at origin/master" >&2 +if [ "$(git rev-parse HEAD)" != "$(git rev-parse origin/main)" ]; then + echo "$(pwd) is not at origin/main" >&2 exit 1 fi From 9659c20ced5fe77824dd5ffd3cdb82175caf318f Mon Sep 17 00:00:00 2001 From: "Sergey \"Shnatsel\" Davidoff" Date: Sun, 19 Jul 2026 23:41:26 +0100 Subject: [PATCH 03/10] Use swizzle_dyn_split for LSX and LASX as well --- crates/core_simd/src/swizzle_dyn.rs | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/crates/core_simd/src/swizzle_dyn.rs b/crates/core_simd/src/swizzle_dyn.rs index 30e6d18451e6c..07d0c1ded1481 100644 --- a/crates/core_simd/src/swizzle_dyn.rs +++ b/crates/core_simd/src/swizzle_dyn.rs @@ -52,6 +52,12 @@ impl Simd { 16 => transize(armv7_neon_swizzle_u8x16, self, idxs), #[cfg(all(target_arch = "loongarch64", target_feature = "lsx"))] 16 => transize(loong64_lsx_swizzle, self, idxs), + #[cfg(all( + target_arch = "loongarch64", + target_feature = "lsx", + not(target_feature = "lasx") + ))] + 32 => transize(swizzle_dyn_split::<32, 16>, self, idxs), #[cfg(all(target_feature = "avx2", not(target_feature = "avx512vbmi")))] 32 => transize(avx2_pshufb, self, idxs), #[cfg(all(target_feature = "avx512vl", target_feature = "avx512vbmi"))] @@ -77,6 +83,8 @@ impl Simd { // Notable absence: avx512bw pshufb shuffle #[cfg(all(target_feature = "avx2", not(target_feature = "avx512vbmi")))] 64 => transize(swizzle_dyn_split::<64, 32>, self, idxs), + #[cfg(all(target_arch = "loongarch64", target_feature = "lasx"))] + 64 => transize(swizzle_dyn_split::<64, 32>, self, idxs), #[cfg(all(target_feature = "avx512vl", target_feature = "avx512vbmi"))] 64 => { // Unlike vpshufb, vpermb doesn't zero out values in the result based on the index high bit @@ -110,7 +118,13 @@ impl Simd { not(target_feature = "avx2"), not(target_feature = "avx512vbmi") ), - all(target_feature = "avx2", not(target_feature = "avx512vbmi")) + all(target_feature = "avx2", not(target_feature = "avx512vbmi")), + all( + target_arch = "loongarch64", + target_feature = "lsx", + not(target_feature = "lasx") + ), + all(target_arch = "loongarch64", target_feature = "lasx") ))] /// Implements an arbitrary shuffle over double the native vector width /// using 4 native-width shuffles From f8aa515d15795524963988b04e2d0bc4d6b5bab4 Mon Sep 17 00:00:00 2001 From: "Sergey \"Shnatsel\" Davidoff" Date: Wed, 22 Jul 2026 08:47:08 +0100 Subject: [PATCH 04/10] #[allow(dead_code)] instead of a humongous cfg --- crates/core_simd/src/swizzle_dyn.rs | 16 +--------------- 1 file changed, 1 insertion(+), 15 deletions(-) diff --git a/crates/core_simd/src/swizzle_dyn.rs b/crates/core_simd/src/swizzle_dyn.rs index 07d0c1ded1481..22ede38373910 100644 --- a/crates/core_simd/src/swizzle_dyn.rs +++ b/crates/core_simd/src/swizzle_dyn.rs @@ -111,21 +111,7 @@ impl Simd { } } -#[cfg(any( - target_feature = "simd128", - all( - target_feature = "ssse3", - not(target_feature = "avx2"), - not(target_feature = "avx512vbmi") - ), - all(target_feature = "avx2", not(target_feature = "avx512vbmi")), - all( - target_arch = "loongarch64", - target_feature = "lsx", - not(target_feature = "lasx") - ), - all(target_arch = "loongarch64", target_feature = "lasx") -))] +#[allow(dead_code, reason = "only used on some targets/features")] /// Implements an arbitrary shuffle over double the native vector width /// using 4 native-width shuffles fn swizzle_dyn_split( From 072095cf12ce56db3400c5fbfcffbd72616ed6ce Mon Sep 17 00:00:00 2001 From: "Sergey \"Shnatsel\" Davidoff" Date: Wed, 22 Jul 2026 09:59:02 +0100 Subject: [PATCH 05/10] Add #[allow(unreachable_patterns)], remove all #[cfg(not(...)] and rely on match branch priority for selecting the best implementation instead --- crates/core_simd/src/swizzle_dyn.rs | 55 ++++++++++++++++------------- 1 file changed, 31 insertions(+), 24 deletions(-) diff --git a/crates/core_simd/src/swizzle_dyn.rs b/crates/core_simd/src/swizzle_dyn.rs index 22ede38373910..36d6bfe1adcfb 100644 --- a/crates/core_simd/src/swizzle_dyn.rs +++ b/crates/core_simd/src/swizzle_dyn.rs @@ -30,19 +30,20 @@ impl Simd { use core::arch::x86_64 as x86; // SAFETY: Intrinsics covered by cfg unsafe { + #[allow( + unreachable_patterns, + reason = "avoids writing verbose cfg(not), earlier branches take priority" + )] match N { + // Aarch64 #[cfg(all( any(target_arch = "aarch64", target_arch = "arm64ec"), target_feature = "neon", target_endian = "little" ))] 8 | 16 | 24 | 32 | 48 | 64 => aarch64_swizzle(self, idxs), - #[cfg(target_feature = "ssse3")] - 16 => transize(x86::_mm_shuffle_epi8, self, zeroing_idxs(idxs)), - #[cfg(target_feature = "simd128")] - 16 => transize(wasm::i8x16_swizzle, self, idxs), - #[cfg(target_feature = "simd128")] - 32 => transize(swizzle_dyn_split::<32, 16>, self, idxs), + + // 32-bit ARMv7 #[cfg(all( target_arch = "arm", target_feature = "v7", @@ -50,16 +51,26 @@ impl Simd { target_endian = "little" ))] 16 => transize(armv7_neon_swizzle_u8x16, self, idxs), + + // WASM SIMD128 + #[cfg(target_feature = "simd128")] + 16 => transize(wasm::i8x16_swizzle, self, idxs), + #[cfg(target_feature = "simd128")] + 32 => transize(swizzle_dyn_split::<32, 16>, self, idxs), + + // LoongArch64 #[cfg(all(target_arch = "loongarch64", target_feature = "lsx"))] 16 => transize(loong64_lsx_swizzle, self, idxs), - #[cfg(all( - target_arch = "loongarch64", - target_feature = "lsx", - not(target_feature = "lasx") - ))] + #[cfg(all(target_arch = "loongarch64", target_feature = "lasx"))] + 32 => transize(loong64_lasx_swizzle, self, idxs), + #[cfg(all(target_arch = "loongarch64", target_feature = "lsx",))] 32 => transize(swizzle_dyn_split::<32, 16>, self, idxs), - #[cfg(all(target_feature = "avx2", not(target_feature = "avx512vbmi")))] - 32 => transize(avx2_pshufb, self, idxs), + #[cfg(all(target_arch = "loongarch64", target_feature = "lasx"))] + 64 => transize(swizzle_dyn_split::<64, 32>, self, idxs), + + // x86, x86-64 + #[cfg(target_feature = "ssse3")] + 16 => transize(x86::_mm_shuffle_epi8, self, zeroing_idxs(idxs)), #[cfg(all(target_feature = "avx512vl", target_feature = "avx512vbmi"))] 32 => { // Unlike vpshufb, vpermb doesn't zero out values in the result based on the index high bit @@ -72,19 +83,11 @@ impl Simd { }; transize(swizzler, self, idxs) } - #[cfg(all( - target_feature = "ssse3", - not(target_feature = "avx2"), - not(target_feature = "avx512vbmi") - ))] + #[cfg(target_feature = "avx2")] + 32 => transize(avx2_pshufb, self, idxs), + #[cfg(target_feature = "ssse3")] 32 => transize(swizzle_dyn_split::<32, 16>, self, idxs), - #[cfg(all(target_arch = "loongarch64", target_feature = "lasx"))] - 32 => transize(loong64_lasx_swizzle, self, idxs), // Notable absence: avx512bw pshufb shuffle - #[cfg(all(target_feature = "avx2", not(target_feature = "avx512vbmi")))] - 64 => transize(swizzle_dyn_split::<64, 32>, self, idxs), - #[cfg(all(target_arch = "loongarch64", target_feature = "lasx"))] - 64 => transize(swizzle_dyn_split::<64, 32>, self, idxs), #[cfg(all(target_feature = "avx512vl", target_feature = "avx512vbmi"))] 64 => { // Unlike vpshufb, vpermb doesn't zero out values in the result based on the index high bit @@ -97,6 +100,10 @@ impl Simd { }; transize(swizzler, self, idxs) } + #[cfg(target_feature = "avx2")] + 64 => transize(swizzle_dyn_split::<64, 32>, self, idxs), + + // scalar fallback _ => { let mut array = [0; N]; for (i, k) in idxs.to_array().into_iter().enumerate() { From 4ca1d7cc4c654218c225c1f8018865028b2a7d32 Mon Sep 17 00:00:00 2001 From: "Sergey \"Shnatsel\" Davidoff" Date: Wed, 22 Jul 2026 10:13:18 +0100 Subject: [PATCH 06/10] remove stray comma Co-authored-by: Jacob Lifshay --- crates/core_simd/src/swizzle_dyn.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/crates/core_simd/src/swizzle_dyn.rs b/crates/core_simd/src/swizzle_dyn.rs index 36d6bfe1adcfb..4894abbf44161 100644 --- a/crates/core_simd/src/swizzle_dyn.rs +++ b/crates/core_simd/src/swizzle_dyn.rs @@ -63,7 +63,7 @@ impl Simd { 16 => transize(loong64_lsx_swizzle, self, idxs), #[cfg(all(target_arch = "loongarch64", target_feature = "lasx"))] 32 => transize(loong64_lasx_swizzle, self, idxs), - #[cfg(all(target_arch = "loongarch64", target_feature = "lsx",))] + #[cfg(all(target_arch = "loongarch64", target_feature = "lsx"))] 32 => transize(swizzle_dyn_split::<32, 16>, self, idxs), #[cfg(all(target_arch = "loongarch64", target_feature = "lasx"))] 64 => transize(swizzle_dyn_split::<64, 32>, self, idxs), From 530ec398d9767b06fa492a9a3e2b85d9a033aced Mon Sep 17 00:00:00 2001 From: "Sergey \"Shnatsel\" Davidoff" Date: Wed, 22 Jul 2026 11:20:44 +0100 Subject: [PATCH 07/10] Optimize swizzle_dyn AVX2 implementation llvm-mca shows no change on Haswell and Broadwell, but Zen 1, Zen 2 and Tiger Lake show a 23% improvement, and a 7-20% improvement on Zen 3. --- crates/core_simd/src/swizzle_dyn.rs | 32 +++++++++++------------------ 1 file changed, 12 insertions(+), 20 deletions(-) diff --git a/crates/core_simd/src/swizzle_dyn.rs b/crates/core_simd/src/swizzle_dyn.rs index 4894abbf44161..db25783057e33 100644 --- a/crates/core_simd/src/swizzle_dyn.rs +++ b/crates/core_simd/src/swizzle_dyn.rs @@ -259,35 +259,27 @@ unsafe fn aarch64_swizzle(bytes: Simd, idxs: Simd) #[inline] #[allow(clippy::let_and_return)] unsafe fn avx2_pshufb(bytes: Simd, idxs: Simd) -> Simd { - use crate::simd::{Select, cmp::SimdPartialOrd}; #[cfg(target_arch = "x86")] use core::arch::x86; #[cfg(target_arch = "x86_64")] use core::arch::x86_64 as x86; use x86::_mm256_permute2x128_si256 as avx2_cross_shuffle; use x86::_mm256_shuffle_epi8 as avx2_half_pshufb; - let mid = Simd::splat(16u8); - let high = mid + mid; // SAFETY: Caller promised AVX2 unsafe { - // This is ordering sensitive, and LLVM will order these how you put them. - // Most AVX2 impls use ~5 "ports", and only 1 or 2 are capable of permutes. - // But the "compose" step will lower to ops that can also use at least 1 other port. - // So this tries to break up permutes so composition flows through "open" ports. - // Comparative benches should be done on multiple AVX2 CPUs before reordering this - - let hihi = avx2_cross_shuffle::<0x11>(bytes.into(), bytes.into()); - let hi_shuf = Simd::from(avx2_half_pshufb( - hihi, // duplicate the vector's top half - idxs.into(), // so that using only 4 bits of an index still picks bytes 16-31 - )); - // A zero-fill during the compose step gives the "all-Neon-like" OOB-is-0 semantics - let compose = idxs.simd_lt(high).select(hi_shuf, Simd::splat(0)); let lolo = avx2_cross_shuffle::<0x00>(bytes.into(), bytes.into()); - let lo_shuf = Simd::from(avx2_half_pshufb(lolo, idxs.into())); - // Repeat, then pick indices < 16, overwriting indices 0-15 from previous compose step - let compose = idxs.simd_lt(mid).select(lo_shuf, compose); - compose + let hihi = avx2_cross_shuffle::<0x11>(bytes.into(), bytes.into()); + + // Adding 0x60 preserves the low nibble and bit 4 for valid + // indices 0..=31. Larger indices get their high bit set, so + // VPSHUFB supplies the required out-of-bounds zeroing. + let control = x86::_mm256_adds_epu8(idxs.into(), x86::_mm256_set1_epi8(0x60)); + + // Move index bit 4 into each byte's sign bit for VPBLENDVB. + let select_high = x86::_mm256_slli_epi16::<3>(control); + let from_low = avx2_half_pshufb(lolo, control); + let from_high = avx2_half_pshufb(hihi, control); + x86::_mm256_blendv_epi8(from_low, from_high, select_high).into() } } From 3b08801efb34a39d3a148538963d4747184db288 Mon Sep 17 00:00:00 2001 From: "Sergey \"Shnatsel\" Davidoff" Date: Sat, 25 Jul 2026 09:42:43 +0100 Subject: [PATCH 08/10] Optimize SSE4.2 as suggested by axnsan12, with an extra OR to preserve correctness for mask values 128-255. Changes the control sequence from vpcmpgtb + vpblendvb to vpaddb + vpor. 15% throughput improvement on Haswell, 20% improvement on skylake, zen1, zen3. For the 256-bit case, 38% improvement on haswell, 12% on skylake, zen1 and zen3 unchanged. Expand test coverage to cover byte values 128-255 which would misbehave without the OR. --- crates/core_simd/src/swizzle_dyn.rs | 7 ++++--- crates/core_simd/tests/swizzle_dyn.rs | 2 +- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/crates/core_simd/src/swizzle_dyn.rs b/crates/core_simd/src/swizzle_dyn.rs index db25783057e33..f0253c284e35f 100644 --- a/crates/core_simd/src/swizzle_dyn.rs +++ b/crates/core_simd/src/swizzle_dyn.rs @@ -338,7 +338,8 @@ unsafe fn transize( #[allow(unused)] #[inline(always)] fn zeroing_idxs(idxs: Simd) -> Simd { - use crate::simd::{Select, cmp::SimdPartialOrd}; - idxs.simd_lt(Simd::splat(N as u8)) - .select(idxs, Simd::splat(u8::MAX)) + // Adding this sets the high bit for indices N..=127, while PSHUFB ignores + // the other changed bits. The OR preserves the high bit for indices 128..=255. + let zeroing_bits = idxs + Simd::splat((127 - N + 1) as u8); + idxs | zeroing_bits } diff --git a/crates/core_simd/tests/swizzle_dyn.rs b/crates/core_simd/tests/swizzle_dyn.rs index 19ffe1417c8c4..4ab6c41c074eb 100644 --- a/crates/core_simd/tests/swizzle_dyn.rs +++ b/crates/core_simd/tests/swizzle_dyn.rs @@ -61,7 +61,7 @@ pub trait SwizzleStrategy { impl SwizzleStrategy for u8 { type Strategy = RangeInclusive; fn swizzled_strategy() -> Self::Strategy { - 0..=64 + 0..=u8::MAX } } From 002cc4fd7897b09d93a53ed0d4963093431252ed Mon Sep 17 00:00:00 2001 From: Folkert de Vries Date: Wed, 29 Jul 2026 15:29:35 +0200 Subject: [PATCH 09/10] test `x86_64-pc-windows-gnu` in CI too --- .github/workflows/ci.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index de7efa3552836..25bc04feab729 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -59,7 +59,7 @@ jobs: strategy: fail-fast: false matrix: - target: [x86_64-pc-windows-msvc, i686-pc-windows-msvc, x86_64-unknown-linux-gnu] + target: [x86_64-pc-windows-msvc, x86_64-pc-windows-gnu, i686-pc-windows-msvc, x86_64-unknown-linux-gnu] # `default` means we use the default target config for the target, # `native` means we run with `-Ctarget-cpu=native`, and anything else is # an arg to `-Ctarget-feature` From 4201a4c6792329f2d6846593afda78b3664d151d Mon Sep 17 00:00:00 2001 From: Folkert de Vries Date: Wed, 29 Jul 2026 15:28:16 +0200 Subject: [PATCH 10/10] gate `std_float` f16 tests --- .github/workflows/ci.yml | 1 + crates/core_simd/tests/f16_ops.rs | 2 +- crates/std_float/Cargo.toml | 8 ++++++++ crates/std_float/tests/float.rs | 4 ++++ 4 files changed, 14 insertions(+), 1 deletion(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 25bc04feab729..759a5337bd826 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -73,6 +73,7 @@ jobs: # Populate the `matrix.os` field - { target: x86_64-unknown-linux-gnu, os: ubuntu-latest } - { target: x86_64-pc-windows-msvc, os: windows-latest } + - { target: x86_64-pc-windows-gnu, os: windows-latest } - { target: i686-pc-windows-msvc, os: windows-latest } # Annoyingly, the x86_64-unknown-linux-gnu runner *almost* always has diff --git a/crates/core_simd/tests/f16_ops.rs b/crates/core_simd/tests/f16_ops.rs index 03e239b745f12..d512ca4e07ba2 100644 --- a/crates/core_simd/tests/f16_ops.rs +++ b/crates/core_simd/tests/f16_ops.rs @@ -2,7 +2,7 @@ #![feature(f16)] #![expect(internal_features)] #![feature(cfg_target_has_reliable_f16_f128)] - +#![allow(unused_features)] #[macro_use] mod ops_macros; diff --git a/crates/std_float/Cargo.toml b/crates/std_float/Cargo.toml index 0896094ee63f4..08360a455b792 100644 --- a/crates/std_float/Cargo.toml +++ b/crates/std_float/Cargo.toml @@ -18,3 +18,11 @@ wasm-bindgen-test = "0.3" [features] default = ["as_crate"] as_crate = [] + +[lints.rust.unexpected_cfgs] +level = "warn" +check-cfg = [ + # Internal features aren't marked known config by default, we use these to + # gate tests. + 'cfg(target_has_reliable_f16_math)', +] diff --git a/crates/std_float/tests/float.rs b/crates/std_float/tests/float.rs index d4d8a90995bce..e0ab7ac4fbd2b 100644 --- a/crates/std_float/tests/float.rs +++ b/crates/std_float/tests/float.rs @@ -1,5 +1,8 @@ #![feature(portable_simd)] #![feature(f16)] +#![feature(cfg_target_has_reliable_f16_f128)] +#![allow(internal_features)] +#![allow(unused_features)] macro_rules! unary_test { { $scalar:tt, $($func:tt),+ } => { @@ -87,6 +90,7 @@ macro_rules! impl_tests { } } +#[cfg(target_has_reliable_f16_math)] impl_tests! { f16 } impl_tests! { f32 } impl_tests! { f64 }