From be8fd0e59186f82318acac9381d304f21f4c715d Mon Sep 17 00:00:00 2001 From: tux3 Date: Sun, 14 Aug 2022 12:09:44 +0200 Subject: [PATCH] feat: Target features for 1st group of RISC-V Bitmanip extensions These use the same names as LLVM and is_riscv_feature_detected!: - zba (address generation instructions) - zbb (basic bit manipulation) - zbc (carry-less multiplication) - zbs (single-bit manipulation) --- compiler/rustc_codegen_ssa/src/target_features.rs | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/compiler/rustc_codegen_ssa/src/target_features.rs b/compiler/rustc_codegen_ssa/src/target_features.rs index ecad0518533ec..9062a83b8be44 100644 --- a/compiler/rustc_codegen_ssa/src/target_features.rs +++ b/compiler/rustc_codegen_ssa/src/target_features.rs @@ -227,6 +227,10 @@ const RISCV_ALLOWED_FEATURES: &[(&str, Option)] = &[ ("zhinxmin", Some(sym::riscv_target_feature)), ("zfh", Some(sym::riscv_target_feature)), ("zfhmin", Some(sym::riscv_target_feature)), + ("zba", Some(sym::riscv_target_feature)), + ("zbb", Some(sym::riscv_target_feature)), + ("zbc", Some(sym::riscv_target_feature)), + ("zbs", Some(sym::riscv_target_feature)), ("zbkb", Some(sym::riscv_target_feature)), ("zbkc", Some(sym::riscv_target_feature)), ("zbkx", Some(sym::riscv_target_feature)),