From 9a65a7023e4076945e0ed884b509053b5e83d13d Mon Sep 17 00:00:00 2001 From: Vadim Kaushan Date: Sat, 14 Mar 2020 11:09:21 +0300 Subject: [PATCH 1/2] Update CHANGELOG.md --- CHANGELOG.md | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/CHANGELOG.md b/CHANGELOG.md index 3eed084e..7aa1ab25 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -7,6 +7,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/). ## [Unreleased] +### Added + +- Added vexriscv-specific registers + ## [v0.5.5] - 2020-02-28 ### Added From 99e189199be352c4cc7fd8507f0381c3a783a087 Mon Sep 17 00:00:00 2001 From: Vadim Kaushan Date: Sat, 14 Mar 2020 11:11:50 +0300 Subject: [PATCH 2/2] Release v0.5.6 --- CHANGELOG.md | 5 ++++- Cargo.toml | 2 +- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 7aa1ab25..7268c846 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -7,6 +7,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/). ## [Unreleased] +## [v0.5.6] - 2020-03-14 + ### Added - Added vexriscv-specific registers @@ -25,5 +27,6 @@ and this project adheres to [Semantic Versioning](http://semver.org/). - Fixed MSRV by restricting the upper bound of `bare-metal` version -[Unreleased]: https://github.com/rust-embedded/riscv/compare/v0.5.5...HEAD +[Unreleased]: https://github.com/rust-embedded/riscv/compare/v0.5.6...HEAD +[v0.5.6]: https://github.com/rust-embedded/riscv/compare/v0.5.5...v0.5.6 [v0.5.5]: https://github.com/rust-embedded/riscv/compare/v0.5.4...v0.5.5 diff --git a/Cargo.toml b/Cargo.toml index 64d8bd70..cfe00a13 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -1,6 +1,6 @@ [package] name = "riscv" -version = "0.5.5" +version = "0.5.6" repository = "https://github.com/rust-embedded/riscv" authors = ["The RISC-V Team "] categories = ["embedded", "hardware-support", "no-std"]